TM4C1294KCPDT: Analog comparator C0+ threshold

Hello BP101,

BP101 said:

This configuration was previously tested via the EK-TM4C1294XL launch pad.

Did it work successfully on the LaunchPad?

Do you have the code from that test still?

Is the only differences from the LaunchPad to your design described by:

BP101 said:

However the three ADC0 inputs had 525 ohm to ground and no 100 ohm isolation resistor between Cn- inputs and ANIx channels.

Seemingly EKLP did work ok with internal VREF ladder setting but had to make VREF 1.3v above the 540mv threshold at Cn- inputs. The Cn- threshold level is now 1.225v and external pot set at 2.3v to stop triggering of c0-, c1-, disabled c02 output into M2Fault input. Can turn the pot up to 2.8v VREF on c0+ and Comp2 still trips. Comp2 may not have worked properly on NCPDT but the c2- threshold was much lower. Seemingly that is why internal VREF+ had to be set well above any actual signal generated trip level.

Mainly 525R lowered Cn- input thresholds to roughly 540mv, being the main difference. Other than each ANIx input; 100R did not exist nor did the 200pf decoupling caps. Figured any decoupling of ANIx from PWM drive would quiet down current samples. Adding 525R to ground source invites PWM pulses to enter the comparators Cn- inputs. Hence we opted for 1.225v external REF1/2 of INA240 to set the ANIx input threshold further then 540mv above ground.

The bigger difference in my mind is KCPDT versus NCPDT. Judging from the symptoms it seems Comp2 ve+ is not made alternate for C0+ VREF on GPIO PC6. Making Comp2 ve+ (PIN) as a test thinking was reversed in figure 22-1 and Co2 trips high on POR, output being inverted.

Perhaps C2 is backwards and does not require inversion and PIN setting could make it work?

Hello BP101,

BP101 said:

The bigger difference in my mind is KCPDT versus NCPDT.

That can't be the root cause, there is no way a change happened in the comparator between those devices.

BP101 said:

Perhaps C2 is backwards and does not require inversion and PIN setting could make it work?

I searched to see if anything like that had been reported and haven't come up with anything that would indicate that.

I would recommend re-visiting the LaunchPad experiment and re-validate if under a normal setup, C2 is able to operate as expected. Once you have reconfirmed that and have confidence in the comparator's functionality, then you can go through your own system step by step to determine what is causing the issue.

Ralph Jacobi said:

I would recommend re-visiting the LaunchPad experiment and re-validate if under a normal setup, C2 is able to operate as expected. Once you have reconfirmed that and have confidence in the comparator's functionality, then you can go through your own system step by step to determine what is causing the issue.

That is sort of the point that the threshold is now much higher in the custom PCB so this anomaly may have been missed by anyone setting Cn- thresholds below 1.225v as we once did. There is no reason the KCPDT MCU analog comparator 2 should be triggering below C0+ set at 2.8v when the other two inputs c0-/c1- thresholds do not trigger via 2.3vdc threshold. Just as we could not use ANI0 due to Eratta #13. So there are known issues with analog inputs that might be effecting custom PCB as the ANIx inputs are not exactly the same due to trace routings. 

Yet it seems the C2- input works but the C2+ input is internally detached from C0+ in register control! One way to prove this issue would be to hot wire the C2+ input pin to the external VREF pot and configure C2- input for external PIN. That is next on list of dam why we have to mess with such things, LOL.

Hi Ralph,

Attempting to reducing the C2- input signal magnitude lower than C1-/C2- signal (1.225v) makes no difference to stop triggering Co2 output at lower thresholds, not effecting C1-/C2- inputs.

It would seem C2 threshold issue existed on EK-TM4C129XL and we unknowingly skirted around it by lowering Cn- signal level (540mv). That signal level well below internal VREF+ ladder divider required VREF+ to be set much higher value as a result. Who would even know unless they disabled Co2 output as we (recently) did, realized lower C0+ threshold is possible with (1.225v) Cn- VREF.

One clue being produced is ADC1 SS0 interrupt stops sampling data on channels AIN9/AIN16, when C2-/Co2 false triggers below C0+ threshold. Assume that too effects AC1 SS1 DCOMP1/DCOMP2 triggering GEN2 internal via M2Fault/Group1. 

Hi BP101,

BP101 said:

It would seem C2 threshold issue existed on EK-TM4C129XL and we unknowingly skirted around it by lowering Cn- signal level (540mv).

Can you please provide the code from re-confirming this issue is also present on the LaunchPad? I can test & debug in lab with our bench supplies if so.

Hi Ralph,

Perhaps when we configured all comparator XOR outputs in OUT direction, false triggering became less an issue for Co2 of EK-TM4C1294XL? Seems past (2015) we had modified Tivaware library call GPIOPinTypeComparator() to use OUT direction versus HW on all EK-TM4C12942XL analog comparator CoN outputs. Can't recall why past that was done other than perhaps it solved some false MoFault triggering in general.

Even so, the Cn- inputs easily tripped Co1,2,3  output just by touching the scope probe,  jumper wires CoN outputs via BP1/2-pins into the three MnFault inputs GEN1,GEN2,GEN3.

Below is the PWM0 Faults configuration:

    /* Configure each PWM genertors minimum fault period (0us).
     * legacy latched minper for digital comparator fault source.
     * Set PWM0 generators M0nFault sense input polarity. */
    MAP_PWMGenFaultConfigure(PWM0_BASE, PWM_GEN_1, 0, PWM_FAULT1_SENSE_HIGH);
    MAP_PWMGenFaultConfigure(PWM0_BASE, PWM_GEN_2, 0, PWM_FAULT2_SENSE_HIGH);
    MAP_PWMGenFaultConfigure(PWM0_BASE, PWM_GEN_3, 0, PWM_FAULT3_SENSE_HIGH);

   /* Configure (OR) extended fault group-0 interrupt sources for M0Fault pins.
    * Assertion to PWM inactive TFaultMax = 40ns, (24ns+1PWMCLK) */
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_1, PWM_FAULT_GROUP_0,
    							(PWM_FAULT_FAULT1|PWM_FAULT_FAULT2|PWM_FAULT_FAULT3));
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_2, PWM_FAULT_GROUP_0,
    							(PWM_FAULT_FAULT1|PWM_FAULT_FAULT2|PWM_FAULT_FAULT3));
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_3, PWM_FAULT_GROUP_0,
    							(PWM_FAULT_FAULT1|PWM_FAULT_FAULT2|PWM_FAULT_FAULT3));

Hello BP101,

GPIODirModeSet(GPIO_PORTD_AHB_BASE, GPIO_PIN_2, GPIO_DIR_MODE_OUT);

That line is wrong. Bob has covered this with you recently, you can't set the comparator output to GPIO_DIR_MODE_OUT and get proper operation. That is why the GPIOPinTypeComparatorOutput calls the GPIODirModeSet within the API and uses the setting of GPIO_DIR_MODE_HW.

That is where your problem is coming from.

Ralph Jacobi said:

That line is wrong

Perhaps I have not made my self clear in this point, do understand it is a confusing topic to relate. If what you say is (entirely) true then why did OUT direction (EK-TM4C1294XL) work for triggering all three comparators configured internal VREF+ for +VEIN. Alternatively issue needs lab work to determine why the OUT direction produces a layer of protection when HW direction does not produce (equal) external C0+ threshold level for all 3 comparators in all classes of TM4C1294x MCU. Agree we should not have 2 comparators working normally in HW direction and the third not working the same way!

There is something wrong with C2- input to reflect C0+ threshold set on PC6 regardless of how C02 is configured. Masking the condition of C2- input seems to stop false triggering Co2 output relative to C0-/C1- for KCPDT MCU set for external VREF+. Again OUT worked for (EK-TM4C1294XL) all 3 comparators set with internal VREF+ and the Cn- inputs threshold remained consistent to equally trigger faults below 1.5vdc. 

The code above is using HW direction for the KCPDT Co0/Co1 configured for LAB analysis as an example only of the current WA revealed for testing EK-TM4C1294XL, not that it is correct. The question remains why does C2- not follow C0+ threshold in the same way as C0-/C1- when set in HW direction with external VREF+ on C0+. Point is the +VEIN threshold (sensitivity) should not (significantly) change between comparators whether configured for internal or external VREF+ sources. 

BTW: The external C0+ VREF is set 2.42VDC to stop C0-/C1- false trigging MnFaults below that high external threshold. Typically we don't add capacitance roll off to the Cn- inputs since it increases the fault trigger time above 1us. We will test adding small capacitance to C2- input to see if it helps reduce sensitivity as adding a pull down R did nothing.

Figured you were going down a false impression path and tried to make clear posted code was a WA to stop false trips. You will need that in the lab or easily get confused by comparator results, symptoms are compounded by the C0+ VREF threshold level relative to signal on Cn- inputs. Wondering if leaving three Cn+ inputs floating (PIN0 configuration) may somehow effect results when a negative pulse excursion is involved.

Perhaps we should tie Cn+/- inputs together versus leaving one pin floating as a WA, solder short adjacent partner MCU pins?

Debug sent to virtual COM port quickly relates analog comparator caused PWMnFault via PWM0 extend fault handling configuration INT25 handler.

You may find code helpful if using PWM0 generators to produce signals as we do. Single codes are 1,2,4 and multiple fault trips produce code 3,5,6,7 respectively.