Hi,
I know this topic has already been discussed in a few topics (e2e.ti.com/.../569566
However I'm still missing an explanation for the source of the problem, so here is my situation.
I'm using a TM4C129 as I2C master. Glitch filter is set to 8 (running at system clock of 120 MHz) with a I2C at 100 kHz
So what I have here is the same situation as described in the other threads with a short SCL pulse:
I know that the signal quality is rather poor and the rise time for the clock is beyond limits.
But what I don't understand is, why the Master aborting the started clock edge and pulling it low. At this point I'm 100% sure the master is holding the SCL lane low, as the slaved use different low levels when they perform clock stretching.
My current assumption is, that the rise time of SCL is too slow for the master and thus it assumes a slave holds the clock low. And then the master holds the SCL low for itself to keep a regular timing for the scl toggling. However I cannot find anything about this behavior in the datasheets.
So can you please confirm my theory or if it is wrong can you explain whyy the TM4C master is holding the clock low after aborting the clock edge?
Many thanks in advance
Fabian