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Hi Lori,

I agree that the code is mostly correct, except for BIT 0. The comment is actually what threw me off.

Thanks for taking another look at this.

Tim

Hi TI support team,

regarding our new Concerto project we need some further information about the bootloader. We're now finishing the schematics design but some connections to the bootloader pins are not clear. We already checked the TRM and the Concerto College documents, especially the Topic 2: System.

1)      We want to flash new Firmware versions to M3 and C28 over UART. If we understood the Slides page 19- 21 we have to make two separate connections. One to the UART0 pins of the M3 and one to the SCI pins of C28. So we need two UART interfaces to the Concerto?

2)      Which GPIO inputs should we connect, because of the possibility of the IO-Multiplexer to change the position of the UART0 and SCIa?

3)       How are the bootloader option pins to configure, for bootloading the M3 and C28?

4)      Which GPIO inputs should we connect, if we want to flash over SPI?

Thanks,

Michael and Andi

Michael and Andi:

Tschech said:

 

Hi TI support team,

 regarding our new Concerto project we need some further information about the bootloader. We're now finishing the schematics design but some connections to the bootloader pins are not clear. We already checked the TRM and the Concerto College documents, especially the Topic 2: System.

 1)      We want to flash new Firmware versions to M3 and C28 over UART. If we understood the Slides page 19- 21 we have to make two separate connections. One to the UART0 pins of the M3 and one to the SCI pins of C28. So we need two UART interfaces to the Concerto?

2)      Which GPIO inputs should we connect, because of the possibility of the IO-Multiplexer to change the position of the UART0 and SCIa?

If you want to boot over UART - Yes you can boot over M3 UART0 and C28 SCI-A. Or you can just boot over M3 UART0, and then have IPC commands copy C28 code into C28 RAM.

GPIO connections:

1. On the M3, connect to UART0 pins: UART0_RX (PA0_GPIO0) and UART0_TX (PA1_GPIO1) - Boot over M3 UART0 using the LM Flash Programmer UART load option to load the .bin binary file (Use TIObj2Bin.exe as post-build step in CCS to convert .out to .bin file). (Application in RAM must start at 0x20005000 because LM Flash programmer expects memory to be contiguous, and boot ROM uses 0x20004000 - 0x20005000 for its own stack/global varables).
2. On the C28, connect to SCI-A pins: SCITXDA (PF3_GPIO35) and SCIRXDA (PF4_GPIO36). Boot over 28x SCI uses same bootloader scheme as previous 28x devices.

Tschech said:

3)       How are the bootloader option pins to configure, for bootloading the M3 and C28?

M3 is the only one which can be booted by GPIO pins:

C28 is booted from the M3 application via IPC commands as follows:

1. M3 application checks CTOMIPCBOOTSTS register to see if CTOM Control System Boot ROM is ready to receive IPC commands (bit 1 set)
2. M3 application loops until MTOCIPC flags 1 and 32 are available (indicating no other IPC command is in progress.
3. M3 application gives C28 control of GPIO pins required for C28 bootloader.
4. M3 application writes "IPC_MTOC_EXECUTE_BOOTMODE_CMD"(0x00000013) to MTOCIPCCOM register.
5. M3 application writes desired boot mode into MTOCIPCBOOTMODE register (see table below)
6. M3 application sets MTOCIPC flags 1 and 32 to cause C28 to execute desired bootloader.

Tschech said:

4)      Which GPIO inputs should we connect, if we want to flash over SPI? 

1. C28 SPI: PD0_GPIO16 (SPISIMOA), PD1_GPIO17 (SPISOMIA), PD2_GPIO18 (SPICLKA), PD3_GPIO19 (SPISTEA) - remember M3 application code must give C28 ownership of above mentioned GPIO pins prior to calling IPC command to boot C28 from SPI.
2. M3: SSI/SPI:  PA3_GPIO3 (SSI0_CS), PA2_GPIO2 (SSIO0_CLK), PA5_GPIO5 (SSI0_TX), PA4_GPIO4 (SSI0_RX).

Concerto Office hour is open again today from 3pm to 4pm Central time.  Keep those questions coming!

Hi Chrissy Chang,

thanks for the very detailed description of the bootloader procedure.

Some more questions to the Concerto device:

Where can we find the IPC commands to copy the C28 Code into the C28 RAM?

On Page 246 in the TRF there are 32 ADC Channels ADC1INA0 to ADC2INB7.  But  on the F28M35H52C1 some of this pins are missing. There are only 16 ADC input pins. On the Evaluation Board four of the ADC-Pins are connected to ground, why? Should we do this with all ADC pins if we don't use them?  

Regards,

 Michael

/*
//###########################################################################
// FILE:    F28M35H52C1_c28.cmd
// TITLE:    Linker Command File For F28M35H52C1 Device
//###########################################################################
// $TI Release: F28M35x Driver Library vBeta1 $
// $Release Date: August 31, 2011 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
// The header linker files are found in <base>\F28M35x_headers\cmd
// For BIOS applications add:      F28M35x_Headers_BIOS.cmd
// For nonBIOS applications add:   F28M35x_Headers_nonBIOS.cmd
========================================================= */

/* Define the memory block start/length for the F28M35x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28M35x are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks or flash sectors can be
         be combined if required to create a larger memory block.
*/

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   
   FLASHN      : origin = 0x100000, length = 0x002000     /* on-chip FLASH */
   FLASHM      : origin = 0x102000, length = 0x002000     /* on-chip FLASH */
   FLASHL      : origin = 0x104000, length = 0x002000     /* on-chip FLASH */
   FLASHK      : origin = 0x106000, length = 0x002000     /* on-chip FLASH */
   FLASHJ      : origin = 0x108000, length = 0x008000     /* on-chip FLASH */
   FLASHI      : origin = 0x110000, length = 0x008000     /* on-chip FLASH */
   FLASHH      : origin = 0x118000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x120000, length = 0x008000     /* on-chip FLASH */
   FLASHF      : origin = 0x128000, length = 0x008000     /* on-chip FLASH */
   FLASHE       : origin = 0x130000, length = 0x008000      /* on-chip FLASH */
   FLASHD      : origin = 0x138000, length = 0x002000      /* on-chip FLASH */
   FLASHC      : origin = 0x13A000, length = 0x002000      /* on-chip FLASH */
   FLASHA      : origin = 0x13E000, length = 0x001F80      /* on-chip FLASH */
   
   CSM_RSVD    : origin = 0x13FF80, length = 0x000070     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x13FFF0, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   FLASH_EXE_ONLY_P0  : origin = 0x13FFF2, length = 0x000002  /* Part of FLASHA.  Flash execute only locations in FLASHA */ 
   ECSL_PWL_P0 : origin = 0x13FFF4, length = 0x000004     /* Part of FLASHA.  ECSL password locations in FLASHA */
   CSM_PWL_P0  : origin = 0x13FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD258, length = 0x0006A0      /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FD8F8, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE448, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE4D4, length = 0x0000AA      /* IQ Math Tables in Boot ROM */

   BOOTROM     : origin = 0x3FEDA8, length = 0x001200     /* Boot ROM */
   PIEMISHNDLR : origin = 0x3FFFBE, length = 0x000002      /* part of boot ROM  */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */
   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */
   RAMS0       : origin = 0x00C000, length = 0x001000     /* on-chip Shared RAM block S0 */
   RAMS1       : origin = 0x00D000, length = 0x001000     /* on-chip Shared RAM block S1 */
   RAMS2       : origin = 0x00E000, length = 0x001000     /* on-chip Shared RAM block S2 */
   RAMS3       : origin = 0x00F000, length = 0x001000     /* on-chip Shared RAM block S3 */
   RAMS4       : origin = 0x010000, length = 0x001000     /* on-chip Shared RAM block S4 */
   RAMS5       : origin = 0x011000, length = 0x001000     /* on-chip Shared RAM block S5 */
   RAMS6       : origin = 0x012000, length = 0x001000     /* on-chip Shared RAM block S6 */
   RAMS7       : origin = 0x013000, length = 0x001000     /* on-chip Shared RAM block S7 */

   CTOMRAM     : origin = 0x03F800, length = 0x000380     /* C28 to M3 Message RAM */
   MTOCRAM     : origin = 0x03FC00, length = 0x000380     /* M3 to C28 Message RAM */
   
   FLASHB      : origin = 0x13C000, length = 0x002000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/

SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA      PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA      PAGE = 0
   codestart           : > BEGIN       PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0

	ramdata             : LOAD = FLASHB,
                          RUN = RAML2,
                          LOAD_START(_RamdataLoadStart),
                          LOAD_END(_RamdataLoadEnd),
                          RUN_START(_RamdataRunStart),
                          PAGE = 1
	                           
                           
   flashexeonly           : > FLASH_EXE_ONLY_P0 PAGE = 0
   ecslpasswds           : > ECSL_PWL_P0 PAGE = 0
   csmpasswds          : > CSM_PWL_P0  PAGE = 0
   csm_rsvd            : > CSM_RSVD    PAGE = 0
   
   /* The following section definitions are required when using the IPC API Drivers */ 
   GROUP : > CTOMRAM, PAGE = 1 
   {
       PUTBUFFER 
       PUTWRITEIDX 
       GETREADIDX 
   }

   GROUP : > MTOCRAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }   
   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML2       PAGE = 1
   .esysmem            : > RAML2       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0
   .switch             : > FLASHA      PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA      PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML2           : > RAML2,       PAGE = 1
   DMARAML3           : > RAML3,       PAGE = 1

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

}

/*
*/

I am trying to run out of c28 flash. It's the cpu timer example. It runs with the IDE, but if I disconnect and power cycle, it does not appear to run (LED no longer flashes.) Attached are the source files. Any suggestions? For the Master, I used something similar to setup_m3 project.

Tim

//###########################################################################
// FILE:   blinky_c28.c
// TITLE:  Blinky Example for F28M35x.
//
//! \addtogroup control_example_list
//! <h1> Blinky (blinky)</h1>
//!
//! This example blinks LED2.
//!
//
//###########################################################################
// $TI Release: F28M35x Driver Library vBeta1 $
// $Release Date: August 31, 2011 $
//###########################################################################

#include "source/DSP28x_Project.h"     // Device Headerfile and Examples Include File

#define C28_FREQ    150         //CPU frequency in MHz

#define FLASH

// These are defined by the linker (see device linker command file)
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;

interrupt void cpu_timer0_isr(void);

void main(void)
{

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F28M35x_SysCtrl.c file.
    InitSysCtrl();

// Step 2. Initialize GPIO:
// This example function is found in the F28M35x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
    InitGpio(); // Skipped for this example
    EALLOW;
    GpioG1CtrlRegs.GPCDIR.bit.GPIO70 = 1; 
    EDIS;
    GpioG1DataRegs.GPCDAT.bit.GPIO70 = 1;// turn off LED
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
    DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F28M35x_PieCtrl.c file.
    InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F28M35x_DefaultIsr.c.
// This function is found in F28M35x_PieVect.c.
    InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.TINT0 = &cpu_timer0_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

// Step 4. Initialize the Device Peripheral. This function can be
//         found in F28M35x_CpuTimers.c
    InitCpuTimers();  // For this example, only initialize the Cpu Timers

//  C28 Freq = 150 MHz. 3rd param is timer period in uSec.
    ConfigCpuTimer(&CpuTimer0, C28_FREQ, 50);

// To ensure precise timing, use write-only instructions to write to the entire
// register. Therefore, if any of the configuration bits are changed in 
// ConfigCpuTimer and InitCpuTimers (in F28M35x_CpuTimers.h), the
// below settings must also be updated.
    CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit
                                    // = 0
                                    //
                                    // 0x4001 is TIE according to Delfino documentation,
                                    // so we are just turning ON CpuTimer0 enable.

// Enable CPU int1 which is connected to CPU-Timer 0
    IER |= M_INT1;
    
// Enable TINT0 in the PIE: Group 1 interrupt 7
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;


    #ifdef FLASH
    // Copy time critical code and Flash setup code to RAM
    // This includes the following ISR functions: EPwm1_timer_isr(), EPwm2_timer_isr()
    // EPwm3_timer_isr and and InitFlash();
    // The  RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
    // symbols are created by the linker. Refer to the device .cmd file.
       MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
    
    // Call Flash Initialization to setup flash waitstates
    // This function must reside in RAM
       InitFlash(); 
    #endif

// Enable global Interrupts and higher priority real-time debug events:
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM


// Step 6. IDLE loop. Just sit and loop forever (optional):
    for(;;)
    {
    }
}




interrupt void cpu_timer0_isr(void)
{
    CpuTimer0.InterruptCount++;

    //Toggle pin 70 for visual confirmation of timer operation
    if(GpioG1DataRegs.GPCDAT.bit.GPIO70 == 0) {
        GpioG1DataRegs.GPCSET.bit.GPIO70 = 1;
    }else{
        GpioG1DataRegs.GPCCLEAR.bit.GPIO70 = 1;
    }

    // Acknowledge this interrupt to receive more interrupts from group 1
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

Tim,

It looks to me like your project is linked correctly to run from Flash, but I suspect your board isn't configured for this type of operation.  Assuming you are on a ConcertoCard, try flipping the first dip switch in SW3.  This will disconnect TRSTn and should allow the processor to run by itself when it boots. 

You will also need to have some type of application programmed into M3 flash as well.  When the chip boots the C28 is initially held in reset.  You need a program on the M3 side to boot and then release the control subsystem from reset.  Check out the setup_m3 project in the control_examples folder.

Trey

Hi Trey,

I flipped dip switch1 on SW3, and it didn't make any difference.

M3 should be working correctly as it blinks the other LED, and the release c28 from reset code is in there. C28 works correctly from Flash when run from the IDE, it's only when I disconnect and power cycle that it does not appear to run.

Tim

Tim,

One more things I forgot...When the C28x boots, it runs a BootROM which services IPC commands.  The C28 will not boot user application code until a "Boot to flash" IPC command has been issued from the M3 to the C28.  The IPC commands should be posted shortly in this thread in response to Michael's question.  When they are posted, try using the boot command to bring up the C28.

Michael,

We haven't forgotten about you :)  I'm working on getting you IPC commands and a response on the ADC question from one of our Analog Gurus.

Full guides for the rest of the peripherals lacking from the TRM should be released soon.

Trey

Thanks for participating in today's Concerto Office Hour.  The final session will be held tomorrow morning (October 6th) from 9 to 10 Central time.

As always though feel free to post anytime to the e2e forums for support from TI experts!

Trey

Hi Chrissy Chang,

I saw, if we configure the bootloader pins of the M3 to boot to the UART0 (line 3 in the boot mode table) also the SSI0 and I2C0 are active.  Is the M3 listening to all these communication pins (UARTO, SSI0,I2C0) at the same time after reset or is there an additional configuration to choose only one communication method? What happens, if we want to boot over UART0 and we have some other digital input signals (from peripheral devices which cannot be influenced directly after reset)  connected to the SSI0 and I2C0? Should we disconnect this pins while the bootloader process is active (or generally not use them) to get the right boot mode behavior to boot only from UART0? 

Regards,

 Michael

Tim -

Your M3 application code needs to boot the C28 from Flash (otherwise the C28 will sit in the boot ROM at IDLE forever).

From your M3 application, be sure to call the following function to boot the C28 from Flash:

IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);

Michael:

I have attached a Word doc with the MtoC IPC commands supported by the C28 boot ROM.

What you will want to do is have the M3 write the C28 code to the Sx shared RAM's.  Then the M3 should use the MSxMSEL bits to give C28 ownership of the Sx shared RAM blocks which you are writing to. Then you can execute the "MASTER_IPC_MTOC_BRANCH_CALL" command to branch to wherever your C28 code begins in Sx shared RAM to begin executing code from the C28.

The order of your code to send an IPC command to the C28 would be:

1. M3 application checks CTOMIPCBOOTSTS register to see if CTOM Control System Boot ROM is ready to receive IPC commands (bit 1 set)
2. M3 application loops until MTOCIPC flags 1 and 32 are available (indicating no other IPC command is in progress.
3. M3 application fills in MTOCIPCCOM/MTOCIPCADDR/MTOCIPCDATAW registers per the attached Word doc table.
4. M3 application sets MTOCIPC flags 1 and 32 to cause C28 to execute desired command.

0882.Concerto_BootROM_MtoC_IPC_commands.doc

Michael,

You are right.  The bootloader sets up all three peripherals and looks for a character on all three of them.  The first one to receive something is selected as teh peripheral for bootloading.

If a valid SPI or I2C message were to be sent before the UART message, the wrong peripheral could potentially be chosen for bootloading.  I doubt I2C will cause an issue because the other device on the bus must be bus master and they must send a message with the correct slave address.  I don't think SPI will be much of an issue either because their must be another master device on the bus and they must pull down Concerto's chip select line.

Regards,

Trey

Tschech said:

Hi Chrissy Chang,

I saw, if we configure the bootloader pins of the M3 to boot to the UART0 (line 3 in the boot mode table) also the SSI0 and I2C0 are active.  Is the M3 listening to all these communication pins (UARTO, SSI0,I2C0) at the same time after reset or is there an additional configuration to choose only one communication method? What happens, if we want to boot over UART0 and we have some other digital input signals (from peripheral devices which cannot be influenced directly after reset)  connected to the SSI0 and I2C0? Should we disconnect this pins while the bootloader process is active (or generally not use them) to get the right boot mode behavior to boot only from UART0? 

Regards,

 Michael

Michael -

Yes, when configured for serial boot load on the M3, the boot loader will scan the UART0/SSI0/and I2C0 ports sequentially and boot from the interface on which it receives data.  If you have other digital signals tied to SSI0/I2C0 pins- either disconnect or tie pins either high or low while the bootloader process is active (ensure these pins are not toggling in such a way that can be interpreted as data being sent to the device).

Hi Chrissy,

I've the following in M3:

// Pull the Control subsystem out of reset

SysCtlReleaseSubSystemFromReset(SYSCTL_CONTROL_SYSTEM_RES_CNF);

IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);

********

Is that sufficient? What's the value of "CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH"?

Thanks,

Tim

Tim,

That should be good.  CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH should be defined to be 2 in MWare\driverlib\ipc.h.

Trey

Michael,

On the F28M35H52C1 device, not all ADC input channels are pinned out because of the amount of pins available in this package.

What four ADC pins are connected to ground?  ADC1VREFLO and ADC2VREFLO should be tied to ground.

Regards,

Ricky

Trey,

It's now stuck at:

unsigned short IPCMtoCBootControlSystem(unsigned long ulBootMode)

{

    // Wait until C28 control system boot ROM is ready to receive MTOCIPC INT1

    // interrupts

    while ((HWREG(MTOCIPC_BASE +

                  IPC_O_CTOMIPCBOOTSTS) &

            CBROM_BOOTSTS_CTOM_CONTROL_SYSTEM_READY)!=

           CBROM_BOOTSTS_CTOM_CONTROL_SYSTEM_READY)

    {

    }

......

}

Do I need to configure the IPC interrupt on C28?

Tim

Hi Ricky,

on the Concerto ControlCard (TMDXCNCDH52C1) ADC pins ADC1B3, ADC1B7, ADC2B3 and ADC2B7 are tied to ground. Because of you dont' use them (no free space on the DIMM-100 connector) or is there any other reason to connected this four pins to ground (no ADC functionality?)?

Regards,

Michael

Hi,

I also got a question about the Bootloader Option Pins on the Concerto ControlCard (TMDXCNCDH52C1). Chrissy Chang posted yesterday the Table M-Boot ROM Boot Mode Table where the usage of GPIO35, GPIO47 and GPIO43 is mentioned. On the Concerto ControlCard there is also GPIO 34 included. Which options are available for this pin?

Regards,

Andi

Michael,

I took a look at the schematics and you are right.  These pins are grounded because there aren't enough ADC pins on the DIM100 connector (which has a standardized pinout across all DIM100 controlCARDs).  You are free to remove the 0 ohm jumpers connected to these pins and use these ADC pins if you want.  We are looking at migrating to a higher pin count card that should mitigate issues like this future.

Trey

I wonder if there is another way of communication between the two MCU rather than sending messages that trigger interrups. Could you please provide us more information? Thank you

Tim,

Well, you can't really configure the IPC interrupt because at this point in the boot process none of your application code has run on the C28.  I think we are doing all of the major things correctly, but I must have overlooked something small which is causing us trouble.  As soon as our bootROM expert gets in this morning I will discuss this problem with him and get back to you.

Trey

Andi,

In future devices GPIO34 is planned to be a boot mode pin, but is not on the F28M35x series of devices.  The state of this pin has no effect on the boot of the device, and the pin can be used for normal GPIO or peripheral activities.

Trey

Miquel,

There are a million ways to send data in between the two MCUs, you just have to be creative :)

The IPC is definitely the preferred and fastest way to move data between the two memory maps.  If you don't want to use interrupts with IPC, they can be disabled and a polling mechanism implemented in software.

There is also a serial loopback that can be turned on between serial peripherals across the two cores (This hasn't been documented yet, but will be soon).  This allows UART4 to talk to SCIA and SSI3 to SPIA.  These modes can be enabled by setting the correct value in the SERLOOP register (look in MWare\inc\hw_sysctl.h for the address).  To enable the UART loopback set bit 8 (0x00000100). To enable SPI loopback with SSI3 as master write 0x00000002 and to enable the loopback with SPIA as master write 0x00000003.

Beyond that you could do an external loopback with two communications peripherals or even use GPIO to transfer data between the two cores.

Hope this helps!

Trey

The final Concerto Office Hour is now open!  Please post your questions below.

Ok Trey, I think I got it, thank you for your fast response, but in case of an access to a same peripherial from both DSP and ARM, let's say ADC for instance, who's got priority? If both were to write in the same register at the same time, does it depend on the OS?

Miquel Massot Campos said:

Ok Trey, I think I got it, thank you for your fast response, but in case of an access to a same peripherial from both DSP and ARM, let's say ADC for instance, who's got priority? If both were to write in the same register at the same time, does it depend on the OS?

Both accesses would use the ACIB bus which uses a round-robin arbitration.  If the 28x and M3 both access the result registers at the same time, the M3 would get priority.  The order of the round robin is:

M3 read -> uDMA read -> c28-read -> C28-write -> c28-dma read/write

Keep in mind the ADC can only be configured by the C28x.  The M3 can only read the result registers.

All other peripherals belong to either the M3 or the 28x subsystem and are not shared.

Regards

Lori

I was checking my Cpu clock setup yesterday and saw something that was puzzling. In the ARM I have:

// Setup main clock tree for 75MHz - M3 and 150MHz - C28x

        SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL |

                         (SYSCTL_SPLLIMULT_M & 0x0F)|SYSCTL_XCLKDIV_4);

And in C28 I have setup CpuTimer0 to interrupt:

ConfigCpuTimer(&CpuTimer0, C28_FREQ, 50);

But when I timed the rising and falling edge, I see 100 usec instead of 50. Some other setting I forgot?

Tim

//###########################################################################
// FILE:   blinky_c28.c
// TITLE:  Blinky Example for F28M35x.
//
//! \addtogroup control_example_list
//! <h1> Blinky (blinky)</h1>
//!
//! This example blinks LED2.
//!
//
//###########################################################################
// $TI Release: F28M35x Driver Library vBeta1 $
// $Release Date: August 31, 2011 $
//###########################################################################

#include "source/DSP28x_Project.h"     // Device Headerfile and Examples Include File

#define C28_FREQ    150         //CPU frequency in MHz

#define FLASH

// These are defined by the linker (see device linker command file)
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;

interrupt void cpu_timer0_isr(void);

void main(void)
{

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F28M35x_SysCtrl.c file.
    InitSysCtrl();

// Step 2. Initialize GPIO:
// This example function is found in the F28M35x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
    InitGpio(); // Skipped for this example
    EALLOW;
    GpioG1CtrlRegs.GPCDIR.bit.GPIO70 = 1; 
    EDIS;
    GpioG1DataRegs.GPCDAT.bit.GPIO70 = 1;// turn off LED
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
    DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F28M35x_PieCtrl.c file.
    InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F28M35x_DefaultIsr.c.
// This function is found in F28M35x_PieVect.c.
    InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.TINT0 = &cpu_timer0_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

// Step 4. Initialize the Device Peripheral. This function can be
//         found in F28M35x_CpuTimers.c
    InitCpuTimers();  // For this example, only initialize the Cpu Timers

//  C28 Freq = 150 MHz. 3rd param is timer period in uSec.
    ConfigCpuTimer(&CpuTimer0, C28_FREQ, 50);

// To ensure precise timing, use write-only instructions to write to the entire
// register. Therefore, if any of the configuration bits are changed in 
// ConfigCpuTimer and InitCpuTimers (in F28M35x_CpuTimers.h), the
// below settings must also be updated.
    CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit
                                    // = 0
                                    //
                                    // 0x4001 is TIE according to Delfino documentation,
                                    // so we are just turning ON CpuTimer0 enable.

// Enable CPU int1 which is connected to CPU-Timer 0
    IER |= M_INT1;
    
// Enable TINT0 in the PIE: Group 1 interrupt 7
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;


    #ifdef FLASH
    // Copy time critical code and Flash setup code to RAM
    // This includes the following ISR functions: EPwm1_timer_isr(), EPwm2_timer_isr()
    // EPwm3_timer_isr and and InitFlash();
    // The  RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
    // symbols are created by the linker. Refer to the device .cmd file.
       MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
    
    // Call Flash Initialization to setup flash waitstates
    // This function must reside in RAM
       InitFlash(); 
    #endif

// Enable global Interrupts and higher priority real-time debug events:
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM


// Step 6. IDLE loop. Just sit and loop forever (optional):
    for(;;)
    {
    }
}




interrupt void cpu_timer0_isr(void)
{
    CpuTimer0.InterruptCount++;

    //Toggle pin 70 for visual confirmation of timer operation
    if(GpioG1DataRegs.GPCDAT.bit.GPIO70 == 0) {
        GpioG1DataRegs.GPCSET.bit.GPIO70 = 1;
    }else{
        GpioG1DataRegs.GPCCLEAR.bit.GPIO70 = 1;
    }

    // Acknowledge this interrupt to receive more interrupts from group 1
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

Tim:

If you are running through the C28 bootloader, you must remove your C28 GEL file and disconnect/reconnect/reset C28. There is a bug in the C28 bootloader that will corrupt the CTOMIPCBOOTSTS value, causing the CTOMIPCBOOTSTS to never reach the CBROM_BOOTSTS_CTOM_CONTROL_SYSTEM_READY state.

The above code has nothing to do with IPC interrupt, and no, when booting, you do not need to configure an IPC interrupt on the C28. The C28 boot ROM  is already configured to receive IPC INT1 interrupts during the boot process.

Hi Chrissy,

Thanks. I did not mean to confuse the two issues (boot & CpuTimer0). My question on CpuTimer0 is a separate issue.

So what happens when I power cycle the Control Card? Will the bootloader bug get in the way?

Tim

Tim11828 said:

I was checking my Cpu clock setup yesterday and saw something that was puzzling. In the ARM I have:

 

// Setup main clock tree for 75MHz - M3 and 150MHz - C28x

        SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL |

                         (SYSCTL_SPLLIMULT_M & 0x0F)|SYSCTL_XCLKDIV_4);

 

 

And in C28 I have setup CpuTimer0 to interrupt:

ConfigCpuTimer(&CpuTimer0, C28_FREQ, 50);

 

But when I timed the rising and falling edge, I see 100 usec instead of 50. Some other setting I forgot?

Tim

4784.main_c28.txt

//###########################################################################
// FILE:   blinky_c28.c
// TITLE:  Blinky Example for F28M35x.
//
//! \addtogroup control_example_list
//! <h1> Blinky (blinky)</h1>
//!
//! This example blinks LED2.
//!
//
//###########################################################################
// $TI Release: F28M35x Driver Library vBeta1 $
// $Release Date: August 31, 2011 $
//###########################################################################

#include "source/DSP28x_Project.h"     // Device Headerfile and Examples Include File

#define C28_FREQ    150         //CPU frequency in MHz

#define FLASH

// These are defined by the linker (see device linker command file)
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;

interrupt void cpu_timer0_isr(void);

void main(void)
{

// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F28M35x_SysCtrl.c file.
    InitSysCtrl();

// Step 2. Initialize GPIO:
// This example function is found in the F28M35x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
    InitGpio(); // Skipped for this example
    EALLOW;
    GpioG1CtrlRegs.GPCDIR.bit.GPIO70 = 1; 
    EDIS;
    GpioG1DataRegs.GPCDAT.bit.GPIO70 = 1;// turn off LED
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
    DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F28M35x_PieCtrl.c file.
    InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F28M35x_DefaultIsr.c.
// This function is found in F28M35x_PieVect.c.
    InitPieVectTable();

// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.TINT0 = &cpu_timer0_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

// Step 4. Initialize the Device Peripheral. This function can be
//         found in F28M35x_CpuTimers.c
    InitCpuTimers();  // For this example, only initialize the Cpu Timers

//  C28 Freq = 150 MHz. 3rd param is timer period in uSec.
    ConfigCpuTimer(&CpuTimer0, C28_FREQ, 50);

// To ensure precise timing, use write-only instructions to write to the entire
// register. Therefore, if any of the configuration bits are changed in 
// ConfigCpuTimer and InitCpuTimers (in F28M35x_CpuTimers.h), the
// below settings must also be updated.
    CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit
                                    // = 0
                                    //
                                    // 0x4001 is TIE according to Delfino documentation,
                                    // so we are just turning ON CpuTimer0 enable.

// Enable CPU int1 which is connected to CPU-Timer 0
    IER |= M_INT1;
    
// Enable TINT0 in the PIE: Group 1 interrupt 7
    PieCtrlRegs.PIEIER1.bit.INTx7 = 1;


    #ifdef FLASH
    // Copy time critical code and Flash setup code to RAM
    // This includes the following ISR functions: EPwm1_timer_isr(), EPwm2_timer_isr()
    // EPwm3_timer_isr and and InitFlash();
    // The  RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
    // symbols are created by the linker. Refer to the device .cmd file.
       MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
    
    // Call Flash Initialization to setup flash waitstates
    // This function must reside in RAM
       InitFlash(); 
    #endif

// Enable global Interrupts and higher priority real-time debug events:
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM


// Step 6. IDLE loop. Just sit and loop forever (optional):
    for(;;)
    {
    }
}




interrupt void cpu_timer0_isr(void)
{
    CpuTimer0.InterruptCount++;

    //Toggle pin 70 for visual confirmation of timer operation
    if(GpioG1DataRegs.GPCDAT.bit.GPIO70 == 0) {
        GpioG1DataRegs.GPCSET.bit.GPIO70 = 1;
    }else{
        GpioG1DataRegs.GPCCLEAR.bit.GPIO70 = 1;
    }

    // Acknowledge this interrupt to receive more interrupts from group 1
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

 

Tim,

At first glance it looks right.  I will need to look closer and get back to you.

This concludes Concerto office hours.  If you have a new question, please start a new post.

Tim,  I'm still looking at your last question.

Tim,

if your program control is stuck there, it means that control subsytem found some error while booting and it is not ready to accept IPC commands.

Can you send us the value that you see in CTOMIPCBOOTSTS registers on M3, when it is stuck waiting for control subsytem ready?

Best Regards

Santosh

Hi Santosh,

I will send that value to you. I am not in the office right now. Give me about an hour.

Tim