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DRV8301: SPIA handle, data loss

Intellectual 320 points

Replies: 6

Views: 435

Part Number: DRV8301

Im trying to communicate with a sepperate controller over SPIA using the F28069M with the DRV8301

The F28069M is behaving as a slave and is reveiving 4x16 bits at a time. This generates 4 interupts for my ISR at a baudrate of 1Mbaud.
This ISR is a different ISR from the mainISR function.

When i set the Run_identify to 0 i do get the full data 95% of the time but the other 5% i get only 3 interrupts in and my data gets out of sync with that.
When i set the Run_identify to 1 it gets even worse. Then i only see vallid data (and 4 interrupts) in 25% of the time.

What can i do to ensure my data integrity stays in tact 100% of the time?

My SPIA setup is shown below.


    SPI_setRxFifoIntLevel(obj->spiAHandle, SPI_FifoLevel_4_Words);
    //SPI_setBaudRate(obj->spiaHandle, SPI_BaudRate_1_MBaud);
    SPI_setCharLength(obj->spiAHandle, SPI_CharLength_16_Bits);
    SPI_setClkPhase(obj->spiAHandle, SPI_ClkPhase_Normal);
    SPI_setClkPolarity(obj->spiAHandle, SPI_ClkPolarity_OutputRisingEdge_InputFallingEdge);
    SPI_setMode(obj->spiAHandle, SPI_Mode_Slave);
    //SPI_setPriority(obj->spiAHandle, SPI_Priority_Immediate);

    PIE_enableInt(obj->pieHandle, PIE_GroupNumber_6, PIE_InterruptSource_SPIARX);
    CPU_enableInt(obj->cpuHandle, CPU_IntNumber_6); // enable SCI CPU interrupt

Thanks for the help!


  • Can you clarify--you say "this generates 4 interupts"--is this 4 interrupts and where each one is for the receipt of 4 words (meaning a total of 16 words)? You're reading 4 words at a time in the ISR, correct? Since you have your FIFO level set to 4 I assume this is the case, but the phrasing confused me a little.

  • In reply to Whitney Dewey:

    Your confusion is valid, because I do receive a total of 4 words (the total length of my buffer). So each interrupt lets me reveive 1 word.

    Now that you are saying it like that, it gets me thinking about how it should be. What you say is that normal practice is that with fifo level 4 i should only receive 1 interrupt every 4 words?
    If so this seems to be an issue at the side of the master?

    In both ways I still don't have a clue why I am losing data (receiving less interrupts).

    This is my test ISR

        int16_t read = 0;
        if (loop < 4){
          read = SPI_read(halHandle->spiAHandle);
          data[loop] = read;
        if (loop >= 4){
          loop = 0;
               //do nothing

  • In reply to Alain van der Kaap:

    Maybe the FIFO is overflowing because you aren't reading the data fast enough and so data is being dropped that way.

    The way you've configured interrupts, you should get an an interrupt when there are 4 words in the FIFO ready to be read, so you may as well read them all at once. Maybe something like this:

    data[0] = SPI_read(halHandle->spiAHandle);
    data[1] = SPI_read(halHandle->spiAHandle);
    data[2] = SPI_read(halHandle->spiAHandle);
    data[3] = SPI_read(halHandle->spiAHandle);


  • In reply to Whitney Dewey:

    If I do that i would read 4 times the same data.
    The only thing SPI_read does is read:  uint16_t data = spi->SPIRXBUF;
    That just 1 16 bit buffer i can read at the time right, after reading it doesnt populate with the next word from the buffer until i get a new interrupt.

    I tried setting a breakpont in my ISR and monitoring the fifostatus

    int16_t rx_flag = SPI_getRxFifoStatus(halHandle->spiAHandle);

    as the program enters the ISR the fifostatus remains 0... This register should inform be about the number of words in the buffer (SPIFFRX) right?

    I think something is going wrong there

    edit: It doens't matter if i set FIFObuffer to 1 word or to 4 words. It looks like it doesn't use the buffer at al. Better to say, it looks like the FIFO settings are not being used at all. Is there something wrong with my setup?

    edit2: I tried debugging on the FIFO status and the SPIFFRX appears to be correct after initialisation i get 0010000000100100b confirming with the datasheet this would be i have correctly set 4 words FIFO with interrupt ennabled. I still do get interrupts but as figure 7 of this ( document shows I'm getting the wrong interrupts (from a non FIFO direction i would assume)

    do i need to dissable somthing to get the FIFO to work?


  • In reply to Alain van der Kaap:

    Can you check the SPIFFENA bit in SPIFFTX? I believe it enables both the TX and RX FIFOs and switches the functionality of the SPIRXINT interrupt as shown in that figure you mentioned.

  • In reply to Whitney Dewey:

    This stumbled me for a whole week.
    How could i have known that an enhanced FIFO bit in a SPI TX register, would be needed to activate the TX FIFO function.

    There is a SPI_enableRxFifo function! why whould this function set that paticular bit.
    Oh well, thanks for the help! It works now.

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