DRV8301: SPIA handle, data loss

Your confusion is valid, because I do receive a total of 4 words (the total length of my buffer). So each interrupt lets me reveive 1 word.

Now that you are saying it like that, it gets me thinking about how it should be. What you say is that normal practice is that with fifo level 4 i should only receive 1 interrupt every 4 words?
If so this seems to be an issue at the side of the master?

In both ways I still don't have a clue why I am losing data (receiving less interrupts).

This is my test ISR

    int16_t read = 0;

    if (loop < 4){

      read = SPI_read(halHandle->spiAHandle);
      data[loop] = read;
      loop++;
    }
    if (loop >= 4){
      loop = 0;
    }
    else{
           //do nothing
    }


    rx_cnt++;
    SPI_clearRxFifoInt(halHandle->spiAHandle);
    PIE_clearInt(halHandle->pieHandle,PIE_GroupNumber_6);

Maybe the FIFO is overflowing because you aren't reading the data fast enough and so data is being dropped that way.

The way you've configured interrupts, you should get an an interrupt when there are 4 words in the FIFO ready to be read, so you may as well read them all at once. Maybe something like this:

data[0] = SPI_read(halHandle->spiAHandle);
data[1] = SPI_read(halHandle->spiAHandle);
data[2] = SPI_read(halHandle->spiAHandle);
data[3] = SPI_read(halHandle->spiAHandle);

rx_cnt++;
SPI_clearRxFifoInt(halHandle->spiAHandle);
PIE_clearInt(halHandle->pieHandle,PIE_GroupNumber_6);

Whitney

If I do that i would read 4 times the same data.
The only thing SPI_read does is read:  uint16_t data = spi->SPIRXBUF;
That just 1 16 bit buffer i can read at the time right, after reading it doesnt populate with the next word from the buffer until i get a new interrupt.

I tried setting a breakpont in my ISR and monitoring the fifostatus

int16_t rx_flag = SPI_getRxFifoStatus(halHandle->spiAHandle);

as the program enters the ISR the fifostatus remains 0... This register should inform be about the number of words in the buffer (SPIFFRX) right?

I think something is going wrong there

edit: It doens't matter if i set FIFObuffer to 1 word or to 4 words. It looks like it doesn't use the buffer at al. Better to say, it looks like the FIFO settings are not being used at all. Is there something wrong with my setup?

edit2: I tried debugging on the FIFO status and the SPIFFRX appears to be correct after initialisation i get 0010000000100100b confirming with the datasheet this would be i have correctly set 4 words FIFO with interrupt ennabled. I still do get interrupts but as figure 7 of this (http://www.ti.com/lit/ug/sprug71b/sprug71b.pdf) document shows I'm getting the wrong interrupts (from a non FIFO direction i would assume)

do i need to dissable somthing to get the FIFO to work?

Alain

ooh...wow.

This stumbled me for a whole week.
How could i have known that an enhanced FIFO bit in a SPI TX register, would be needed to activate the TX FIFO function.

There is a SPI_enableRxFifo function! why whould this function set that paticular bit.
Oh well, thanks for the help! It works now.