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DRV10983: Minimum fall/rise time on the SCL/SDA line?

JuMar
Prodigy 530 points
Part Number: DRV10983

Hello,

For a customer of mine I received this question: 

Could you tell me whether there is a minimum fall/rise time on the SCL/SDA line?

They are facing some I2C issues between FPGA used as master and the driver.

When decreasing the current strength of the FPGA outputs on the SCL/SDA lines the problem seems to be fixed.

By doing this the fall time is going from 1.62ns to 7.5ns

Thanks in advance for you help

  • 0
    TI__Expert 6065 points

    Hey JuMar,

         I am not as well-versed in I2C so I need to talk to team to verify. This is my immediate thoughts so far that I need to verify:

    I think NXP (Formerly Phillips)  created I2C and the NXP I2C protocol description is here (www.nxp.com/.../UM10204.pdf).  This is according to this website (www.i2c-bus.org/.../). I believe we follow "fast-mode" i2c since our similar device scl clock frequency is max 400kHz, and the corresponding min fall time is 20ns*(Vdd/5.5V)..

    You switching fall time from 1.62ns to 7.5ns leading for the communication to work kind of makes sense because you are getting closer to the minimum spec of I2C. I would recommend switching to a slower fall time to make it fit the spec 20ns*(Vdd/5.5V). 

    Let me know if this helps and meanwhile i'll confirm with my team.

  • 0 in reply to Sanmesh Udhayakumar
    Prodigy 10 points

    Hello Sanmesh,

    I am the customer who asked that question.

    I am aware about these specifications but I assumed that the DVR was following the standard mode where the minimum tr/tf is not clearly specified. So if you can confirm the fast-mode is support it would definitely clarify the problem.

    Regards,

    Stephane

  • 0 in reply to Stephane Gheeraert
    TI__Expert 6065 points

    Hey Stephane,

    I talked to our design team and we recommend 100kHz I2C clock frequency and the min fall time for SDA is 10ns (Cb <50pf) when driven by DRV10983.

    Sincerely,

           Sanmesh U.