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DRV8704: Device Failure Cause

Stephen Serlenga
Prodigy 170 points
Part Number: DRV8704
Other Parts Discussed in Thread: CSD19531Q5A

Hello,

I was wondering if the support team could offer some advice on a design where we are implementing the DRV8704 into a TEC (Peltier) driver system. To achieve this, the outputs (xOUT1 and xOUT2) from the MOSFET bridge are LC low-pass filtered (yet to be optimised). Depending on the complementary duty cycle of the PWM inputs to the DRV8704 (an inverter is used on a single PWM signal to provide true commentary inputs), the DC output has a bipolar swing from 0V differential voltage through to almost the full VM (PVIN: +48V) across the outputs. So, each output will have ½ of VM applied to it for a 50/50 duty cycle into the device. The MCU is not generating the PWM signals but has control over if they are in-phase or are inverted, and if they get sent to the DRV8704 or not (can be disabled).

I have attached schematic captures of the DRV8704 driver, bridge, and output filters. The SLEEPn line can be assumed to always be pulled high in fixed hardware, the RESET line is controlled by an MCU (internal pullup enabled), however currently this has no external pullup on. I am aware the DRV8704 has an internal pulldown on this pin. The PCB layout is fashioned as the one recommended in the datasheet. I have a six-layer PCB where the gate drive traces via straight from the device pins into an internal layer and are widened.

I have a prototype board where I have implemented this circuit. Sometimes the DRV8704 asserted it’s FAULTn pin upon power-up (applying VM and applying +3V3 to SLEEPn). I didn’t get chance to read the status register unfortunately. The device and the four MOSFETs died after only a very small amount of testing was completed. It seems the driver chip has popped a hole in its plastic casing, close to the charge pump area / HS drive. The four MOSFETs have also died, however I am not sure if it was the FETs that killed the driver or the driver that took out the FETs (I assume the latter). The driver was using all default register settings at the time, with a PWM input frequency of 200kHz. A 10-ohm load was connected across the outputs at the time. Initially I assumed a shoot-through event, however the MOSFETs seems to mainly have failed from a gate-source over-voltage (almost as if the full VM has been applied to them):

Q7: G-S short.

Q8: G-S short.

Q10: G-S short. D-S short.

Q9: G-S short. 1k D-S.

 My first question is, can you clarify the safest way to boot the driver up as the datasheet doesn’t seem to give this information. I assume that VM should first be applied, with the device held in SLEEPn and RESET (to make sure the H-bridge is disabled). The fact that both SLEEPn and RESET have internal pulldowns suggest that it is safe for the device to power up out of reset mode. When my device died, I had the following procedure:

-          Boot up (apply VM), SLEEPn pulled to +3V3.

-          Pull RESET line low (so device is awake, charge pump is active, and device is waiting for PWM inputs).

-          Wait two seconds.

-          Send complementary PWM inputs to AIN1 and AIN2.

I can’t be sure what the duty-cycle of the PWM inputs were at the time, but I am relatively confident the device died AFTER the two second wait. I think the device needs a strong pullup on the RESET line, so the device doesn’t bounce around when the MCU is programmed etc; I suspect this could damage the drivers and FETs. Could it be of any danger to provide large differences in duty-cycle to the inputs while the device is brought out of reset? Could the device or MOSFETs be at risk if the RESET pin is toggled while PWM is still being applied to the inputs (for example would the OCP circuitry still be active during the RESET toggle?).

I can’t see any obvious issues in driving the CSD19531Q5A FETs with the default register setup, even at 200kHz. I think it may be wise to change the VCP capacitor from a 16V to say a 50V capacitor however. Or it could be possible that the LC filtering itself had something to do with the failure.

I've also attached a scope capture of the driver driving the four FETs (on a different board before this fault was experienced). Does the charged-pumped rise time look normal on the HS outputs (around 200ns for the ~12V charge pump voltage to driver the HS FETs).

Apologies for the quantity of questions and the long post, but there may be something obvious that I am missing here.

Thank you for any advice that can be offered.

Kind Regards,

Stephen

 



 



  • 0
    TI__Guru 56650 points

    Stephen,

    I didn't find something obvious wrong in your circuit and test waveform. Now, we have to step by step debug it.

    1. I think I can understand the attached waveform (gate voltage for each FET). Please clarify the measurement point of each scope channel.

    2. When the part gets damage,  either the voltage over stress or current/heat over stress can kill the part. We need to catch the abnormal waveform before the part damage:

    Over current stress check:

    a. When the part and FETs get damage, what is the motor temperature?

    b. Would you check the OCPTH and OCPDEG setting? Each cycle time is 5us when the switching frequency is 200kHz. With 50% duty cycle, the high side FET turn-on time is only 2.5us.

    If OCPDEG setting is too long, the part cannot have the OCP or current control, that could cause the damage.

    Over voltage stress check:

    a. Would you reduce the input to 24V and do the same test and monitor the FET Gate to Source voltage? Does it have any overstress event? If not, can we step by step increasing the input voltage?

    b. DRV part is enabled before the input signal is ready. Please check AIN1; AIN2 and output during the start up.

  • 0 in reply to Wang5577
    Prodigy 170 points

    Hi Wang, thank you for your response.

    You are correct in thinking that the oscilloscope capture is from the four MOSFETs, probed at the MOSFET gate nodes.

    Regarding over current stress check: I was driving the LC filtered outputs into a 10-ohm resistive load and the driver / FETs died instantly when the PWM inputs were enabled so unfortunately, I didn’t have chance to record the temperatures. The OCPTH and OCPDEG settings were at the defaults (500mV threshold, 2.1us deglitch time).

    Regarding over voltage stress check: I will have to modify some other hardware on the board to be able to run at lower voltages; 24V won’t be possible but ~28V should be. I will perform these modifications and then test again on another channel, measuring the high-side FET gate to source voltage.

    I now have a concern over the OCPDEG settings – does this mean I need to limit the maximum applied duty-cycle for a given input frequency? Otherwise like you say, the driver cannot have OCP as the HS FET minimum turn-on time will be less than the OCP deglitch time. So, to allow a suitable deglitch time, as an example for an input frequency of 200kHz and setting the OCPDEG to 2.1us, we can have 42% duty-cycle minimum (period * duty-cycle %), and for 1.05us OCPDEG we can have 21% duty-cycle minimum?

    Is the OCP threshold a function of the RDS(on) of the MOSFETs?

    Since my current setup can apply the up to 95% - 5% duty-cycle to the inputs, I will likely have to reduce the frequency. I shall modify another board for use with a lower input voltage and then report my findings.

    Kind Regards,

    Stephen

  • 0 in reply to Stephen Serlenga
    TI__Guru 56650 points
    Stephen,

    First, we want to check how high the current can go in OCPDEG. If it is too high, we may have to change the design to limit the peak current. For example:
    If the OCPDEG is 2.1us; the inductor is 10uH; the input voltage is 48V and assume the LC filter output doesn't change to much in 2.1us, the output current could rise I= V*t/L=48*2.1/10= 10A. If you use a small inductor, the current could be even higher and the inductor may be saturated which cannot limit the output current.

    What is the peak current value in your design?
  • 0 in reply to Wang5577
    Prodigy 170 points
    Hi Wang,

    The maximum output current on this particular channel is up to 10A. The inductors on this channel are rated at 9.2uH, 12A RMS, 10.5A Saturation current. The test setup then could theoretically allow up to 10.96A at 48V with a 2.1us deglitch time, which would then put the inductor into saturation.

    Kind Regards,

    Stephen
  • 0 in reply to Stephen Serlenga
    TI__Guru 56650 points
    Stephen,

    Now, I think we understand the issue and find the root cause.
    Delta I= Vin * Ton/ L. To avoid the issue, we have to reduce input or OCPDEG or increase L.
  • 0 in reply to Wang5577
    Prodigy 170 points

    Thank you for your help.

    I think two things can be done to protect the system in future:

    1) Let the PWM inputs settle around 50% duty-cycle before inverting one of the signals.

    2) Most importantly, increase the inductance value with a saturation current that can tolerate the RMS load current plus the peak ripple, but also the RMS load current plus the current inrush produced within the 1.05us OCP deglitch time, to protect against a fault event. This would mean that even at extreme duty-cycles, while the device OCP may not have enough time to react compared to the FET on-time, the increased inductance would prevent the current ever rising to the saturation value within this time. Obviously the MOSFETs must be able to tolerate this also.

    I shall mark the thread as resolved.

    Kind Regards,

    Stephen