Part Number: DRV8305-Q1
My customer would like to monitor nFAULT=Low to High changing status during power-up
and then, start SPI communication for resister setting.
So I would like to make sure several as below. Please give your advice.
1. nFAULT Delay, across PVDD_UVLO2 to nFAULT=>High.
The situation is diffrent, but tPD, E-SD is defined as max. 1us.
I guess max. 1us would be enough as this kind of delay.
How do you think?
2. tSPI_READY is defined as max. 10ms. It is after PVDD>VPVDD_UVLO1.
The customer will monitor the change state nFAULT Low to High.
I guess max. 10ms delay would be safer starting SPI communication.
How do you think?
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Anuj Narain:
Thank you so much for your advice.
I will follow tSPI_READY (10ms).
How much time would be reasonable as nFAULT Delay,
across PVDD_UVLO2 to nFAULT => High?
Of course, You don't need to assure that.
In reply to hideyuki sakai:
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.