Is the power block on the chip NFETS for both hi and lo sides? The block diagram shows a PMOS on the high side along with a bootstrap. The use of a bootstrap and PMOSdidn’t make sense to me unless the high side was drawn as PMOS in error.
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Is the power block on the chip NFETS for both hi and lo sides? The block diagram shows a PMOS on the high side along with a bootstrap. The use of a bootstrap and PMOSdidn’t make sense to me unless the high side was drawn as PMOS in error.