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DRV8860: DRV8860 Serial Communication

Part Number: DRV8860

What is the advantage of the custom protocol used with the DRV8860? Why not use a standard protocol?

  • This device's data throughput is 8 bits, while other serial protocols utilize more (e.g. 16 bits).
  • What is the advantage to that?
  • The advantages are, when compared to a serial protocol command, like SPI, and if both clock frequencies are the same, are:

    1. SPI requires 16 bits per transaction, while this protocol requires 8 bits per transaction (twice the throughput). which leads to the second point:

    2. For every daisy chained device, you would need 2x the clock cycles to reach the end device the data is being written to.

  • Hi Hector,

    Thanks for that response. I see how the increased payload with SPI can add up when daisy chaining devices.

    Is there a reference to application code to test with the DRV8860? I have already implemented a library on an STM32 micro using mbedOS, but I'm curious how others have been able to do this - more specifically using an RTOS. I'm able to do this using a completely event driven architecture and there are far more efficient APIs than mbed, but it seems like it is necessary to bit bang out the proper read/write sequence of the '8860 and then it is possible to do the data transfer with a SPI peripheral. These days days I'm only familiar with PICs, Nordic and STM32, but in each of these platforms it's necessary to initialize the SPI port and then deinitialize it in order to do the bit banging of the any pins assigned to a SPI port( the clock line in this case). From an RTOS perspective, this seems like much more overhead than allowing a SPI port to send out a few more bytes.

    Am I looking at this the wrong way?

    Thanks.

  • Hi Stephen,

    The source code can be found in the DRV8860EVM_MSP430_FIRMWARE.zip file in the Hardware files of the DRV8860EVM.

    The direct link is: http: //www.ti.com/lit/zip/slvc596

    You can look further into it to determine if it meets your functional requirements.