• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 435 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV10987: SPEED-Analog Mode

hideyuki sakai
Mastermind 6250 points
Part Number: DRV10987

Dear, Sir.

My customer will start the design to apply DRV10987 for their system.

In advance, they would like to make sure following topics.

Please give your advice.

1. Full-speed voltage & Zero-speed Volatge.

   It will be defined on the datasheet, 0.1V to 0.9* 3.3v.

   I am not sure the real resolution of internal ADC, but I wonder the

  lower reading values & higher reading values would be conveted to Full & Zero?

2. Resolution.

  It will be defined, typ. 6.5mV.

  I wonder the resolution will be reflected the error like INL, DNL?

  If you know like ENOB, Please advice me.

Best Regards,

H. Sakai

  • 0
    TI__Expert 6065 points

    Question 1)  "I wonder the lower reading values & higher reading values would be converted to Full & Zero?"

    Answer 1) If the voltage is in the range of "Analog zero-speed voltage" spec,  then it will be zero speed/duty cycle.  If the voltage is in the range of "Analog full-speed voltage" spec,  then it will be full speed/100% duty cycle. But there are two duty cycle profile modes which you can select as shown below and in the datasheet.

    Question 2) "I am not sure the real resolution of internal ADC is". What is effective number of bits? (ENOB)

    Answer 2) Like you mentioned, the analog voltage resolution is 6.5mV typical. As per ENOB, I will have to check, but I would guess around 9 bits, since 3.3V/6.5mV = 507, and 2^9 = 512. I need to check if that calculation is correct.

  • 0 in reply to Sanmesh Udhayakumar
    Mastermind 6250 points

    Dear, Sanmes-san. 

    Thank you so much for your advice. give your advice one more time. 

    Regarding  2), Could you please give your advice, one more time. 

    **************************************************************************

    Answer 2) Like you mentioned, the analog voltage resolution is 6.5mV typical. As per ENOB,

    I will have to check, but I would guess around 9 bits, since 3.3V/6.5mV = 507, and 2^9 = 512. I need to check if that calculation is correct.

    **************************************************************************

    Best Regards, 

    H. Sakai

  • 0 in reply to hideyuki sakai
    TI__Expert 6065 points
    Dear H. Sakai-san,

    Because the ADC accuracy is not listed as a spec in the datasheet, I cannot give an ENOB. However:
    1) if you want to get rid of the adc error, you can control speed through PWM control or use I2C control, which should both be extremely accurate. All speed control methods have a resolution of 6.5mV/3.3V or 10/511, which is almost 0.2% resolution.
    2) Lets assume even if you throw away the first 3 bits out of the 9 bits, you would still have a duty cycle resolution of (6.5e-3V/3.3V)*2^3 *100% = 1.6% duty cycle accuracy. You can decide if this accuracy is good enough for you or whether this is a good estimate for you on ENOB.

    Sincerely,
    Sanmesh U.
  • 0 in reply to Sanmesh Udhayakumar
    Mastermind 6250 points

    Dear, Sanmesh-san.

    Thank you so much for all of your teachings.

    My customer would like to analog input by resistor divided voltage.

    So I would like to ask additional, Please teach me one more time.

    1. Is it no problem to input resistor divided voltage on SPEED pin?

    2. Regarding DRV10987D,  VEX_SL is defined min. 2.2V.

       Is it correct value?

    3. RPD_SPEED_SL is defined min. 55kOHM. this pull-down is effective

       for other mode not only Sleep mode?

    4. They will use 3.3V LDO output The other side, full & zero-speed ratio &

       value are defined on datasheet. Does it mean the speed threshold will

       have the variation due to input voltage shift?

    Best Regards,

    H. Sakai

  • 0 in reply to hideyuki sakai
    TI__Expert 6065 points
    Let me get back to you on these questions.
  • 0 in reply to Sanmesh Udhayakumar
    Mastermind 6250 points
    Dear, Sanmesh-san.

    Sorry to ask you so many things.
    They will start the design within short time, so many questions are coming.

    I am hoping to get your help, one more time.

    Best Regards,
    H. Sakai
  • 0 in reply to hideyuki sakai
    TI__Expert 6065 points
    Q1. Is it no problem to input resistor divided voltage on SPEED pin?
    A1. Its fine. Just keep in mind the internal speed pin pulldown resistance might affect your resistor network.

    Q2. Regarding DRV10987D, VEX_SL is defined min. 2.2V.
    Is it correct value?
    A2. yes it is correct. If you're concerned about it further, let me know why so I may help you.

    Q3. RPD_SPEED_SL is defined min. 55kOHM. this pull-down is effective for other mode not only Sleep mode?
    A3. I believe so.

    Q4. They will use 3.3V LDO output The other side, full & zero-speed ratio & value are defined on datasheet. Does it mean the speed threshold will have the variation due to input voltage shift?
    A4. Correct me if my assumption is wrong. My understanding is you are using 3.3V LDO output as voltage source for the resistor divider. And your question is regarding the consistency of duty cycle commands given from the analog speed control when you have variation from the 3.3V LDO and variation from the the "Analog full-speed voltage" and "Analog zero-speed voltage" voltage values. You are correct that there might be slight variation. Just keep in mind that the ADC reading the analog voltage has resolution of 6.5mV. For more precise duty cycle control if that's desired, I would use pwm speed control or i2c speed control.