• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 2 answers
  • Subscribers 29 subscribers
  • Views 526 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV10987: Current Limit

hideyuki sakai
Mastermind 6250 points
Part Number: DRV10987

Dear, Sir. 

The current limit is explained on the datasheet, section 8.4.8.1. 

I wonder the method will be monitor the current immediately or monitor

VDS voltage on FET? 

Sorry to ask this kind of matter, but Please give your advice. 

Best Regards, 

H. Sakai

  • 0
    TI__Expert 6065 points
    Let me check with my coworkers. Is your assumption that current wont be monitered immediately by a VDS voltage monitor on the FET?
  • 0 in reply to Sanmesh Udhayakumar
    Mastermind 6250 points
    Dear, Sanmesh-san.

    Sorry to ask you so many things.
    They will start the design within short time, so many questions are coming.

    I am hoping to get your help, one more time.

    Best Regards,
    H. Sakai
  • 0 in reply to hideyuki sakai
    TI__Expert 6065 points
    I think the current limit lock measures current through current sense I believe, and the Overcurrent limit is measured by Vds monitor I think, but I need to confirm. I apologize for not getting back to you on this sooner.
  • 0 in reply to Sanmesh Udhayakumar
    TI__Expert 6065 points
    Current limit is done with current sense (current mirror)
  • 0 in reply to Sanmesh Udhayakumar
    Mastermind 6250 points
    Dear, Sammesh-san.

    I am feeling a mount of gratitude for all of your strong support.
    I understood the method of Current limit(CL), Thank you so much.
    At last, I would like to make sure one thing relating CL.

    As you know, the discrete part like FET has the break-down area.
    SOA(Safety Operating Area) is existing not to reach to such break-down area
    with some marginal zone.

    DRV10987 is embed the driver & has CL function(max. 5.5A). This value would
    be determined not to reach the break-down area.
    My customer would like to know how much margin would be expected?
    They would like to make sure DRV10987 is designed well considering about
    SOA standing point.

    The exact value is not needed, the rough range is enough.
    Please give your advice if you have & Sorry to ask about this kind of matter.

    Best Regards,
    H. Sakai
  • 0 in reply to hideyuki sakai
    TI__Expert 6065 points
    the current rating of the fets is around 10A. So you should have good margin in current.
  • 0 in reply to Sanmesh Udhayakumar
    Mastermind 6250 points

    Dear, Sammesh-san. 

    My customer is asking about the accuracy of Lock-Detection Current Limit &

    Software Current Limit. So I would like to make sure following. 

    1. Lock-Detection Current Limit

    a)According the resister setting, the minimum step is 0.4A. 

       I wonder the accuracy(error) will be included in this step. 

       If so, Could you please clarify the ration of error on 0.4A. 

    b)If not so, Could you please let me know the accuracy(error) on this CL. 

    2. Software Current Limit.

    a)According the resister setting, the minimum step is 0.2A. 

       I wonder the accuracy(error) will be included in this step. 

       If so, Could you please clarify the ration of error on 0.2A. 

    b)If not so, Could you please let me know the accuracy(error) on this CL. 

    Please give your advice. 

    Best Regards, 

    H. Sakai

  • 0 in reply to hideyuki sakai
    TI__Expert 6065 points

    Regarding the hardware current limit, we dont have these accuracies in the datasheet spec so we cant guarantee them. 

    As per the software current limit, that is more of an estimate, and doesnt measure current directly. Instead it estimates current using the equation VU_LIMIT = ILIMIT × RPH_CT + Speed × Kt and solving for ILimit.