Hi team,
I would like to know DRV8323R must use 47nf cap between CPH and CPL pin. What about 50nf?
Thanks!
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Hi team,
I would like to know DRV8323R must use 47nf cap between CPH and CPL pin. What about 50nf?
Thanks!
Eggsy,
Regards,
-Adam
Hi Adam,
Thanks for your help!
Yes, they use independent mode and they just need AB two phase. They use the HS and LS of each phase. Just show the LS part in SCH.
The application is UPS from 48V DC to 220 AC.
Thanks!
Hi Adam,
My customer have test their board based on DRV8323H. In the SCH, We know it is Full bridge Circuit.
VM=50V, If D=50%, RSM of output voltage is 25V between SHA and SHB. The load is "transformer"
But they met some problems which DRV8323H is broken when transformer's output voltage is up to 25V.
If transformer's output voltage is smaller than 25V, DRV8323H work find.
And if the load is changed from transformer to resistance, it work find even though output voltage is up to 25V.
May I know why?
We also do the another test. If gate resistance R30 value is changed from 10Ω to 60Ω, DRV8323H work find even though output voltage is up to 25V with transformer.
May I know why ?
Thanks!
Eggsy,
The issue here is that if the IDRIVE is too high or the gate resistance is too low, the Gate and Source nodes will have excess ringing with overshoot and undershoot. This will cause excessive chip heating and potentially damage the IC. The damage is not due to the heat but actually due to the overshoot and undershoot exceeding the ABS MAX of the device pins.
Does the customer require gate resistors? If not, they can remove these gate resistors and we can calculate the needed IDRIVE strength for them. This will save them board space and components.
Regards,
Adam Sidelsky
Littelfuse_Discrete_MOSFETs_N-Channel_Trench_Gate_IXFP110N15T2_Datasheet....pdf
Hi Adam,
we did a test. Let IDriver=1A, gate resistors=45 Ω.Independence mode.The SCH have been showed in above post.
Below pic is waveform and MOS datasheet. Pink one is high side MOS Vds; Blue one is high side MOS Vgs; Yellow one is low side MOS Vds.
We can see, the high side MOS Vds is unstable due to high side MOS Vgs Shock, which cause low side MOS Vds overshoot, up to 184V.
So it is terrible. But when reducing the load, the waveform is better.
Do you have any suggestions to deal with it?
And is it helpful when reducing Idriver or improving gate resistors?