DRV8412: Details on the PWM Inputs in Each Mode

Hi Steve,

Would you please confirm the modes you are mentioning are the hex equivalent of the M3, M2, M1 pins? Further in the datasheet (section 7.4), the modes are described as modes 1 through 4.

Also this section describes the operation of the inputs vs outputs.

From Section 7.4 (with a few additional comments about Mode 3

Modes 1 and 2, PWM_x controls OUT_x  When PWM_x is low, OUT_x is low. When PWM_x is high, OUT_x is high

Mode 3, PWM_A controls OUT_A and OUT_B, and PWM_B controls OUT_C and OUT_D.

When PWM_A is low, OUT_A and OUT_B are low
When PWM_A is high, OUT_A and OUT_B are high
When PWM_B is low, OUT_C and OUT_D are low
When PWM_B is high, OUT_C and OUT_D are high

Mode 4, PWM_A controls OUT_A and OUT_B, and PWM_C controls OUT_C and OUT_D.

When PWM_A is low, OUT_A is low and OUT_B is high.
When PWM_A is high, OUT_A is high and OUT_B is low.
When PWM_C is low, OUT_C is low and OUT_D is high.
When PWM_C is high, OUT_C is high and OUT_D is low.

Please note the description in the section describing how to recover from a output that has been disabled by the cycle by cycle limit.

If I understand your desired connections for driving 3 TECs cold-only, it is possible to do so. But there are constraints with both the RESET_xx and cycle by cycle limits.

From section 7.4: during parallel mode when /RESET_AB or /RESET_CD are low, all four outputs are hi-Z. Also, if one pair (OUT_A/OUT_B or OUT_C/OUT_D) reach the cycle by cycle limit, both pairs will enter hi-Z until both PWM_A and PWM_B are cycled.

Thanks for the reply and info, Rick.  Yes, my post is referencing the Mode Selection binary code.  I did notice that section 7.4 uses Mode 1-4, but the Mode Selection table doesn't have this reference so it was uncertain and went with good 'ol binary.  I must prefer table info given my requests for them in my post.  If the datasheet gets revised, adding a Mode Number column on the Mode Selection Pins table would clarify this. 

Your statements on the PWM vs. outputs are exactly what I was looking for.  Thanks!  

I'll look into the cycle-by-cycle limit recovery.

From your info it looks like for the cold-only TECs I can use mode 3 (parallel full bridge) and connect Out_A  to Out_B (with separate series inductors that I need to smooth the TEC current anyway) and Out_C  to Out_D.  I would use PWM_A with the OUT_A/B H-bridge for one TEC and the other signals for the other independent TEC.  I'm not sure what to do with the 3rd TEC - use half of another DRV8412 or a different solution.  Will this solution work?  I could also use Mode 1 (4 H-bridges) and connect the 4 PWMs and 4 Outputs together in pairs appropriately, but Mode 3 is more straightforward.  Please let me know if there are benefits to using Mode 1 instead.  I'll have to dig deeper into the cycle-by-cycle concern - I must prevent any shutdown from happening or a 3-day automated process will be ruined.

Can you supply more info on power dissipation since that's the limiting parameter for these motor drivers (~5W to keep the die below shutdown).  The DRV8873 datasheet has explicit power calculation equations, including switching power.  Will the same equations work for the DRV8412, maybe with some parameter adjustments?  For a single DRV8412 H-bridge the Rds-on is very similar, and that power is easy to calculate anyway.  In my case, the DRV8873 switching power is between 50% and 100% of the Rds-on power, depending on the details of frequency, slew rate, voltage (24V in my case), etc. so switching power is very significant and eliminates the DRV8873 for my 3A TEC applications.  The  DRV8412 supports a faster PWM so I would expect the switching power to be different (lower?), so any power calculation details would be greatly appreciated.  

Hi Steve,

From your info it looks like for the cold-only TECs I can use mode 3 (parallel full bridge) and connect Out_A  to Out_B (with separate series inductors that I need to smooth the TEC current anyway) and Out_C  to Out_D.  I would use PWM_A with the OUT_A/B H-bridge for one TEC and the other signals for the other independent TEC.  I'm not sure what to do with the 3rd TEC - use half of another DRV8412 or a different solution.  Will this solution work?

Yes, this solution should work. Mode 3 is more straightforward as you mentioned. The cycle by cycle is intended as a first level of current limitation. It has a 20% device to device variation, so it is typically recommended to set it such that it does not activate. Setting the cycle by cycle limit so that it does not normally activate also prevents OUT_A/B and OUT_C/D interfering with each other.

For the 3rd TEC, using Mode 3 makes sense. You can use OUT_A/B to drive the third TEC. If your high current TEC is cold only, the second DRV8412 may also work with both a cold only and the high current connected OUT_C/D.

Another possible option for cold only is to use MODE 1 (000) with one half bridge connected to each of the 3 cold only TECs. This is especially true if only two of the three are active simultaneously.

The power calculation for the FETs is similar, but there are some additional losses to consider. For 24V, assume the quiescent losses are ~600mW. This includes the IVgvdd and IPvdd currents.

For 80kHz, the switching losses are approximately 200mW.

Great info, Rick.  Thanks.

The PWM frequency is a trade-off between the LC filter, dynamic current, and switching power generation.  Can you give me the switching power for 100k, 200k, 300k, 400k, and 500k?  I need to see the trends and then simulate what I gain at the higher frequencies (like smaller inductors) and where I lose on the power dissipation side.  (Or an equation so I can calculate them.)  Thanks.