This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: DRV2700
I have some troubles with noise ripple on the dc boost BST side of the DRV2700. Attached you find the layout and the schematics of the circuit.
I have programmed the dc boost voltage at 68,4V (rms) with the resistor voltage divider. In the screenshot from the oscilloscope measurement (osci_output.png) you can imagine, that on the boost dc voltage (BST pin) (yellow signal) is a ripple of Vpp=12,8V.
The magenta and the cyan signals are the out+ and out- signals (pins) . The differential voltage of the output signals is the piezo signal with Vpp=125V. Due to the differential measurement, the ripples are not present in the violet signal nevertheless, there is still some audible noise radiated by the piezo. I think there is anywhere a mistake in the circuit, because the ripple on the dc boost is extremely high.
I didn't find anything to modify on your schematic or layout. However, I would suggest to increase the Boost Capacitor. As mentioned in section 220.127.116.11.5 of datasheet ( http://www.ti.com/lit/ds/symlink/drv2700.pdf#page=16 ). In order to achieve a smaller ripple, you must increase the capacitance level. I cannot recommend a specific value since the layout capacitance may be also added. But please try increasing the capacitor value in 20nF steps (or any other more accessible value for you).
Please let me know how it results.
Best regards,Luis Fernando Rodríguez S.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Luis Fernando Rodriguez S.:
Thanks for the suggestion. I increased the boost capacitor in small stepps up to 330nF, without any change in the ripple behaviour.
In reply to Mario Theissl:
Thank you for testing this. Is it possible to try reaching 1uF capacitor value? Do you have some differences?
In addition, some capacitors from OUT+ and OUT- to GND can help to reduce the ripple. Could you try using capacitors values from 10nF to 1uF, please? They should be enough to reduce the ripple considerably.
Do you have any update on this? Do you have more observations?
I will close this E2E thread for now. But please feel free to add your feedback about this case if you have additional information.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.