DRV8353RH-EVM: About the dead time.

Kengo,

Thanks for posting on the MD forum!

The VDS setting does not effect the deadtime, this is only for setting the trip point for the VDS overcurrent protection.

The device uses the actual Vgs measured to decide if the FET is ON or OFF.

Please measure and provide the gate and source waveform of the affected FET and post it here so we can analyze.

Regards,

-Adam 

Adam.

Thank you for your reply.

I made a typo.

VDS -> VGS

So, my question is 

1.What value should the VGS voltage be set to start the dead time?

What is the VGS voltage to determine whether the FET is on or off?

Sincerely.

Kengo.

Kengo,

I am looking into this and will get back to you by tomorrow EoB.

Regards,

-Adam

Kengo,

The Vgs monitors consider ~1.5V the ON/OFF point for the FETs.

Regards,

-Adam

Adam.

Thank you for your answer.

We got a wave form with a sharp Vgs.

*The dead time setting is 400ns.

It seems that there is a divergence from the set time.

Could you tell me why ?

Sincerely.

Kengo.

Kengo,

Could you explain which signal is the HS and which is the LS? 

Can you show a phase current for this half bridge? We want to see if the current is coming into or out of the bridge at the time the dead time is extended.

Regards,

-Adam

Adam.

Thank you for your reply.

I'd like to know bellow questions about you said.

1. I think the rules(as bellow fig) about the dead time.

   There has been a lot of extra dead time since the LS turned off.

   Is the HS fluttering a problem when turned on?

2. Why do you need the a phase current wave form?

    I don't fully understand the relationship with the dead time.

3. Is there a factor other than Vgs that automatically adjusts the dead time?

Sincerely.

Kengo.

Kengo,

I am checking if the following situation applies in this case:

Only Vgs is used to automatically adjust the dead time but as you can see above, this case might be the cause.

Regards,

-Adam

Adam.

Sorry for my late reply.

I ask to my customer to get wave forms as your request.

Please tell me additional question.

Is this additional delay 200nsMAX?

Sincerely.

Kengo.

Kengo,

Yes 200nS is expected max.

Regards,

-Adam

Adam.

Thank you for your reply.

I understood it is the maximum value for additional dead time.

However I think there is a difference between the customer's waveform and your comments.

Could you give me your advice about the remaining additional dead time?

Sincerely.

Kengo.

Hi Adam.

How about my question?

I'll wait for your answer.

Sincerely.

Kengo.

Kengo,

Sorry for the delay. 

Can you confirm that the waveform you showed is measured from the Gate differentially to the source?

Regards,

-Adam

Adam.

I'm sorry I was not clear.

This waveform is measured using the isolation probe between the gate and source.

Sincerely.

Kengo.

Kengo,

Can you measure the Vgs voltage very close to the DRV and post a screenshot?

Currently it looks like the measurement is made at the FET and the DRV will only be monitoring the signals near the DRV.

Regards,

-Adam

Adam.

I'll check to a customer.

I'd like to know one more thing.

The dead time is typical value.

How much is the variation?

Sincerely.

Kengo.

Adam.

How about my question about the dead time value for SPI.

By the way, I asked a customer to get a waveform, but it was refused.

Why do you need to measure the Vgs voltage very close to the DRV ?

SIncerely.

Kengo.

Kengo,

Since the DRV will dynamically adjust the dead time based on the Vgs voltage seen at the pins of the IC, if there is a difference between the FET Vgs and the Vgs seen near the IC then the dead time will appear wrong. The DRV can only control the deadtime based on the Vgs at the actual IC pins.

Regards,

-Adam

Adam.

Thank you for your explain.

I understood.

I'll ask the customer to measure.

And then, how do you think about the variation in the set value of SPI dead time?

I think this is included in variation the dead time.

Sincerely.

Kengo.