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DRV8305-Q1: WAKE & EN_GATE Low to High delay time after PVDD Poser-up

hideyuki sakai
Mastermind 6250 points
Part Number: DRV8305-Q1

Dear, Sir.

My customer is about following questions.

Sorry to disturb your job, but Please give your advice.

1. Is there the deday time definition on WAKE signal low to high after PVDD power-up?

2. Is there the delay time definition on EN_GATE signal low to high after PVDD power-up?

Best Regards,

H. Sakai

  • 0
    TI__Guru 61360 points

    Hideyuki,

    Thanks for posting on the MD forum!

    1. The wake signal is not valid until the device is placed in Standby mode and it has then been put into the sleep mode through SPI. Even when the PVDD is fully up, the wake signal is still not useful until sleep mode is used.

    2. EN_GATE cannot operate until after the digital core is active which depends on the bring up of DVDD. Once DVDD is active then the EN_GATE signal can be used.

    Regards,

    -Adam

  • 0 in reply to Adam Sidelsky
    Mastermind 6250 points

    Dear, Adam-san. 

    I am feeling a mount of gratitude for your valuable information. 

    I understood your mentioning. I would like to verify a few including additional. 

    Please give your advice one more time. 

    1. The customer is using DRV83055Q. It has the PWRGD output(open drain). 

      Can EN_GATE operate soon after PWRGD Low to High? 

    2. About VDRAIN, It will be the power supply for the internal VDS comparators. 

      Is there any violating supply timing against PVDD ramp-up, EN_GATE low to high

      or something else?

    Best Regards, 

    H. Sakai

  • 0 in reply to hideyuki sakai
    TI__Guru 61360 points

    Sakai,

    Sorry about the delay.

    1. Yes they can.
    2. The PVDD will have undervoltage protection so only once this is cleared would the EN_GATE work to turn on the gate output.

    Regards,

    -Adam