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DRV8323: Digital input deglitcher delay

Prodigy 40 points

Replies: 7

Views: 43

Part Number: DRV8323

Hi

we are study the datasheet of DRV8323 and have a question about the digital input deglitcher delay.

In datasheet, it mentioned that The propagation delay time (tpd)  has three parts consisting of the digital input deglitcher delay, the digital propagation delay, and the delay through the analog gate drivers.

So seems there is a digital mask time of INx pins. May i know the mask time (the digital deglitcher delay) so we can check our MCU output signals may cause deglitch or not.

best regards

  • Wang,

    Thanks for posting on the MD forum!

    I have forwarded your request to my team and hope to have an answer for you this week.

    Regards,

    -Adam

  • In reply to Adam Sidelsky:

    Wang,

    The inputs of the DRV832x are checked on the rising and falling edge of the internal 50MHz clock. This means the "sample and hold" time should be about 1/100MHz or 10nS. This is also the minimum PWM ON pulse time.

    Regards,

    -Adam

  • In reply to Adam Sidelsky:

    Hi Adam

    Thank you for the answer. 

    so it means  any  L or H level longer than 10nS will be responded, right?

    > This is also the minimum PWM ON pulse time.

    excuse me for a additional question,  I would like confirm what "PWM ON pulse time" means.

    for example, in 3 PWM mode, a high pulse in INHx will turn on GHx, does the "PWM ON pulse time" means the H period of GHx?

    In detail,  if a  10nS high pulse signal is inputted into  INHx, is the excepted behavior as follows?

     - GLx start changing to L after t(PD) and goes to L at (PD) + t(DRIVE) of L side.

     - GHx start changing to H after t(PD) + t(DRIVE) of L side + t(DEAD) and goes to H at  t(PD) + t(DRIVE) of L side + t(DEAD) + t(DRIVE) of H side

     - GHx start changing to L after t(PD) + t(DRIVE) of L side + t(DEAD) + t(DRIVE) of H side  + 10nS

    best regards

  • In reply to Wang Xiaoming:

    Wang,

    Yes your understanding is correct.

    Your expected behavior is correct but the gate may not take the complete TDRIVE to slew from H to L or L to H. Deadtime is also adjustable since the driver is monitoring the gate and will automatically adjust the dead time based on the gate signal.

    My comment about the minumum PWM ON pulse time is mentioned because many customers want to know what the minimum duty cycle is based on their PWM frequency.

    Regards,

    -Adam

  • In reply to Adam Sidelsky:

    Hi Adam

    thank you for your reply and excuse me for continue question.

    1. You mentioned that gate may not take completer TDRIVE and deadtime is also autmatically adujested,

    From the datasheet, gate voltage will be monitored reach Vgs threshold or not, and form previous post, you mentioned the threshold is 2V.

    do you means IC will always monitor Vgs and when Vgs cross 2s, TDRVIE will be finished and move to TDEAD as figure 27 in datasheet.

    And datasheet shows that TDEAD is selectable but does not mentions it is automatically adjusted, any threshold monitor the Vgs to adjust TDEAD?

    or the deadtime you mentioned in about means total time of   changable TDRIVE + fixed TDEAD.

    2. when drive gate from L to H,  2V threshold seems good to detect GDF,

    if TDRIVE stop when Vgs cross 2V, it seems not high enough to turn on FET fully.

    or the IC have another threshold for L to H transition? 

     

    best regards 

  • In reply to Wang Xiaoming:

    Wang,

    There is both a fixed dead time and a variable dead time. 

    The TDRIVE does not stop once we cross the ~2V value on the gate, TDRIVE continues until the gate is fully charged, the TDRIVE expires, or if the input command changes before the TDRIVE expires.

    Regards,

    -Adam

  • In reply to Adam Sidelsky:

    Hi Adam

    thank you for the confirm.

    best regards