• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 426 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8702-Q1: Input Capacitance on the PH_IN1 and EN/IN2 pins

Robert Cohen
Prodigy 80 points
Part Number: DRV8702-Q1

I am using the DRV8702-Q1 Evaluation board and have successfully connected it to my micro controller.    In order to keep my firmware the same from my previous motor driver I used a couple of FETs  (See schematic below) to process the PWM signal before they are sent to the motor controller.

What is the input capacitance in PH_IN1, EN/IN2 pins?   I looked through the entire spec.

>The value calculated from my signal captures (See below) seemed excessive at 6600pF.

Instead of using FETs I am thinking of using a AND gate. This may be a better interface to the motor controller.

What are your thoughts on the best interface?

Thank you,

Rob Cohen

 

  • 0
    TI__Guru 56650 points
    Rob,

    I don't think the IC input capacitance on PH_IN1, EN/IN2 pins can be 6600pF that high. It should be much less than that. If you test it on an EVM, you can modify R24 and R25 and quickly find it out.
    In your FET logic circuit, IN1 and IN2 pins are also connected to FET's gate or other circuitry. That makes the signal slow and makes you think the INx pin input capacitance high.

    The logic circuit can avoid the FET's gate capacitance on INx pin. But, please double check: is any other circuitry also connected to INx?
  • 0 in reply to Wang5577
    Prodigy 80 points

    Wang5577,

    We came up with a better design for the input circuit. We used an AND gate as shown below.  We did this because we did not want to rewrite a lot of firmware.

    This really cleaned up the signals. See the wave form below.

    I am working on the PCB layout and am limited to the layout space. I was hoping to move the driver closer to the FET and also adding more thermal holes to get the heat off the board. Below is my approach.   Do you see any problems with this?

    The evaluation board is working great. I am glad I bought two. The second one been very helpful in my general needs for motor testing and evaluation.  

    Thank you,

    Rob

  • 0 in reply to Robert Cohen
    TI__Guru 56650 points
    Rob,
    Your layout plan is good to me. Great to hear the EVM working great. I will pass your comment to the EVM designer.