Hi Guys,
I would like to know more on the OMAP 4460 GPMC function.
My interest is to investigate the possibilities of GPMC interface with DUAL PORT DDR RAM(Cypress's FullFlex36). Also, TI can Dual port DDR RAM?
As for OMAP 4460's GPMC address pin[1:16], & data pin[0:15] are multiplexed. Another is address pin[17:26], which is not multiplexed. my target on the interface is a dual port sram using the part below: 1. Cypress's CY7C008v/ CY7C018v ( Address pin [0:15] & & data pin: [0:7] ) 2. IDT's IDT48097.(Address pin [0:13] & data pin: [0:7] ) Here is my question, assume we are going to use Cypress's(16 bits address & 8bits databus) Is it possible to connect as following: 1. Address pin [0:15] convert to data pin: [0:7], so we have left address pin [8:15](8pins) 2. Convert the leftover address pin [8:15](8pins) remap it as address pin[0:8] 3. Then address pin[17:23] remap it to serves as address pin[9:16]?
Hello Jason,
I have attached an application note that talks about interfacing dual-port Cypress memory to OMAP using its GPMC interface. This App note was written for OMAP2xxx, but its concept is applicable to OMAP4.
Regards,
Shaheen0005.Cypress Dual Port to TI OMAP.pdf
One thing I forgot to mention, it can support dual port SDRAM but not DDR SDRAM
Hi Shaheen, Thanks for the apps notes! It is kinda weird to find why GPMC must be mux between data and address bus. The Reason we selected OMAP4 because currently this is the only TI ARM that is dual core and almost similiar to the ipad alike spec. On top of that, with pandaboard's GPMC is expanded out for user to play around, not to forget it is a well supported android community. My current solution is to use CY7C009V.(128K x 8) There will be an interface between dual port sram - OMAP, using FPGA/PLA to decode/mux the address and bus. for the high data streaming image dump. This is something we are trying to solve.
Can you please help out?
Hi Shaheen,
Thanks for the apps notes!
This is the only TI ARM that is dual core and almost similiar to the ipad alike spec. On top of that, with pandaboard's GPMC is expanded out for user to play around, not to forget it is a well supported android community. My current solution is to use CY7C009V.(128K x 8) There will be an interface between dual port sram - OMAP, using FPGA/PLA to decode/mux the address and bus.
As for the high data streaming image dump. This is something we are trying to solve.
Can you please start another thread for high data streaming image dump?
Thank you,
Magdalena
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