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TI Home » TI E2E Community » Support Forums » OMAP™ Applications Processors » OMAP 4 Forum » Accessing the cache memory in omap4430 !!!
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Accessing the cache memory in omap4430 !!!

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studinstru sggs
Posted by studinstru sggs
on May 16 2012 04:30 AM
Expert1870 points

Hi,

I want to access the omap4430 cache memory (32kb :I && 32kb : D cache).

How i will access this memory through instructions or code ?????

-Studinstru

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  • Ranjith Parakkal
    Posted by Ranjith Parakkal
    on May 16 2012 06:36 AM
    Prodigy390 points

    Cortex A9 Cache memory(both L1D and L1P) is not addressable. So you cannot read the contents of the cache memory.

     

    You can only turn on the caches and you should see a visible improvement in your performance. If you are using Linux or Android, then you can be assured, that these caches are already getting enabled somewhere. If you are trying to run ARM-BIOS or some OS like that on Cortex A9, you may have to call some specific API to enable it.

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  • studinstru sggs
    Posted by studinstru sggs
    on May 18 2012 15:58 PM
    Expert1870 points

    Thanks Ranjith.

    Can u give more explanation on linux based platform...?

    such that which api to use......etc..

    your guidance will definitely help me

    -studinstru

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  • Ranjith Parakkal
    Posted by Ranjith Parakkal
    on May 21 2012 03:06 AM
    Verified Answer
    Verified by studinstru sggs
    Prodigy390 points

    On Linux there are no cache related APIs available on the user side. The cache would be getting set somewhere in the kernel during boot-up time.  I dont know the exact APIs. But you can be sure that on OMAP4 data cache and instruction cache are already getting set in Linux. However there are some memory regions like tiler buffers where data caching is disabled.

     

    What exactly is your usecase. Why do you need cache APIs ? That will help me answer you better.

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