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TI Home » TI E2E Community » Support Forums » OMAP™ Applications Processors » OMAP 4 Forum » Memory alignment problem while using LDR instruction in cortex A9
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Memory alignment problem while using LDR instruction in cortex A9

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Angel Mary Nathan
Posted by Angel Mary Nathan
on Aug 03 2012 08:18 AM
Prodigy40 points

Hi,

I am facing some problem while trying to load a 32 bit value into a register by using LDR R0 [R1] where R1 is a pointer to a memory location having some value.
when i use the LDR instruction 3bytes are fetched from the location pointed by R1 and the 4th byte is 1st byte before the loacation pointed by R1.
I am working on ARM Cortex A9 simulator.
Is it anything related to memory alignment?
How do i solve this?

Thanks in advance
Angel 

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  • Gina Glaser
    Posted by Gina Glaser
    on Aug 03 2012 09:27 AM
    Verified Answer
    Verified by Magdalena Iovescu
    Expert8055 points

    Angel,

    Since this is a question specific to the ARM Cortex A9 simulator, I suggest you redirect this to the ARM support forums.

    Thank you,
    Gina 

    Please click the Verify Answer button on this post if it answers your question

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  • Angel Mary Nathan
    Posted by Angel Mary Nathan
    on Aug 06 2012 01:40 AM
    Prodigy40 points

    Thanks Gina.

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  • Gina Glaser
    Posted by Gina Glaser
    on Aug 06 2012 11:37 AM
    Expert8055 points

    Angel,

    Thanks, could you please click "verify answer" for this thread?

    Thanks,
    Gina 

    Please click the Verify Answer button on this post if it answers your question

    _______________________________________________________

    Be sure to read the OMAP4 and OMAP5 Forum Guidelines and FAQ 

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