OMAP 4 Forum - Recent Threads

Booting blaze tablet for the first time

Michael Sogo — Wed, 22 May 2013 17:29:03 GMT

Hi,

I have a blaze tablet 4460 ES.1.1 GP 1.5Ghz and I am trying to boot it for the first time.

I used the pre-build binaries of 4AJ.2.5 release and I used the release notes from this link: http://www.omappedia.com/wiki/4AJ.2.5_OMAP4_Jelly_Bean_Release_Notes.

I repartitioned my SD card with "Alternative Script to format SD Cards for 3 partitions" from this link: http://omappedia.org/wiki/Android_Build_SD_Configuration ,and copied MLO of 4AJ.2.5 release and after unamount and amount the u-boot.bin as well. Both of the files were copied to Boot partition.

I set the switch OFF ON OFF ON ON ON OFF ON so it will boot from SD, and connected the blaze tablet with both micro and mini USB to the computer. It is connected to AC power as well and the battery/Off/AC power switch is set on AC power.

I use minicom to communicate with the tablet. I set the port to be /dev/ttyUSB2 and 115200 as the baudrate, 8 data bits, 1 stop bit as advised by Gina Glaser in this link; http://e2e.ti.com/support/omap/f/849/t/188749.aspx?pi239031349=2.

when I try to boot the blaze tablet a green light is blinking. according to the links below it means that the blaze tablet successfully got in to fastboot. links; http://e2e.ti.com/support/omap/f/849/t/188749.aspx?pi239031349=2 , http://e2e.ti.com/support/omap/f/849/t/227315.aspx

My problem is that I don't see any messages in the minicom. I think I should see something right?

I tried to continue release note instructions:

./fastboot oem format
   ./fastboot flash xloader ./MLO
   ./fastboot flash bootloader ./u-boot.bin

after that the I set the first and the third switch on and tried to boot the blaze tablet. It didn't boot.

What am I doing wrong? Please help!

Thanks
Michael S.

Splash Screen using UBoot for LCD (DPI and no DSI)

Gregory St-Jean100117 — Tue, 21 May 2013 13:35:55 GMT

Hi all,

I modified the TI code from http://review.omapzoom.org/#/c/23975/ for displaying the logo on LCD using DPI and no DSI when Uboot is running. Unfortunately I have not managed to see the output signal DISPC2_PCLK (pin W4 of the OMAP 4460). What is the missing in my code ?

We plan to start production this summer. I need to fix this issue before.

Thank you for your support.

Gregory

(Please visit the site to view this file)

GPIO interrupt on DSP Tesla vs. M3 Ducati (OMAP4)

GregoireGentil — Thu, 23 May 2013 00:39:20 GMT

The following simple BIOS/Syslink code works on Cortex-M3 Ducati:

Hwi_Params hwiParams;
Error_Block eb;
Hwi_Params_init(&hwiParams);
Error_init(&eb);
hwiParams.arg = 0;
hwiParams.eventId = 10;
hwiParams.maskSetting = Hwi_MaskingOption_SELF;
hwiParams.enableInt = TRUE;
Hwi_create(GPIO1_IRQ, IsrGPIO1, &hwiParams, &eb);
if (Error_check(&eb)) {INFO("Error\n");}
Hwi_enable();

while it doesn't work on DSP Tesla (GPIO1_IRQ = 73 there):

[ 4.956] [t=0x000b76d3] ti.sysbios.family.c64p.Hwi: ERROR: line 511: E_handleNotFound: Hwi handle not found: 0x90110448
[ 4.956] ti.sysbios.family.c64p.Hwi: line 511: E_handleNotFound: Hwi handle not found: 0x90110448
[ 4.956] xdc.runtime.Error.raise: terminating execution

Any idea what I'm missing? I don't understand why BIOS is trying to delete a HWI. Many thanks in advance for any advice.

wifi problem

mukesh thakur1 — Tue, 14 May 2013 08:49:27 GMT

A) From where i should get the firmware for OMAP4 ICS ??

git clone git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git (Showing :read error:connection reset by peer)

B) Actually while booting the TI blaze Tablet it showing Error could not get firmware:2

Help me to resolve these two.

Regards

Mukesh

use ISP on pandaboard('CSI2A –> IPIPEIF –> MEM')

achun liu — Fri, 17 May 2013 06:56:32 GMT

hi,

I use your omap4-v4l2-camera branch on pandaboard,I use ov8810,the output format is 8/10/12 bit raw rgb,I choice 8 bit, now i can capture image successfully(link to CSI2A) use command:

media-ctl -r
media-ctl -l '"OMAP4 ISS CSI2a":1 -> "OMAP4 ISS CSI2a output":0 [1]'
media-ctl -V '"ov8810 3-0036":0 [SBGGR8 1920x1080]'
media-ctl -V '"OMAP4 ISS CSI2a":0 [SBGGR8 1920x1080]'

yavta -c4 -n3 -fSBGGR8 -s1920x1080 -Ftest-#.rgb /dev/video0

when I try 'CSI2A –> IPIPEIF –> MEM' use command:

media-ctl -r -l '"OMAP4 ISS CSI2a":1 -> "OMAP4 ISS ISP IPIPEIF":0 [1]','"OMAP4 ISS ISP IPIPEIF":1 -> "OMAP4 ISS ISP IPIPEIF output":0 [1]'
media-ctl -V '"ov8810 3-0036":0 [SBGGR8 1920x1080]','"OMAP4 ISS CSI2a":0 [SBGGR8 1920x1080]','"OMAP4 ISS ISP IPIPEIF":0 [SBGGR8 1920x1080]'
yavta /dev/video2 -c4 -n1 -s1920x1080 -fSBGGR8 -Fov8810-1920x1080-#.bin

the generated file, all data is 0,I don't know this is why,the fllow is my register debug:

[   96.365966] omap4iss omap4iss: -------------IPIPEIF Register dump-------------
[   96.366027] omap4iss omap4iss: ###IPIPEIF CFG1=0x00000000
[   96.366027] omap4iss omap4iss: ###IPIPEIF CFG2=0x00000000

[   96.366027] omap4iss omap4iss: ###ISIF SYNCEN=0x00000001
[   96.366058] omap4iss omap4iss: ###ISIF CADU=0x00000000
[   96.366058] omap4iss omap4iss: ###ISIF CADL=0x00000000
[   96.366058] omap4iss omap4iss: ###ISIF MODESET=0x00002000
[   96.366088] omap4iss omap4iss: ###ISIF CCOLP=0x00000000
[   96.366088] omap4iss omap4iss: ###ISIF SPH=0x00000000
[   96.366088] omap4iss omap4iss: ###ISIF LNH=0x0000077f
[   96.366119] omap4iss omap4iss: ###ISIF LNV=0x00000437
[   96.366119] omap4iss omap4iss: ###ISIF VDINT0=0x00000437
[   96.366119] omap4iss omap4iss: ###ISIF HSIZE=0x0000003c
[   96.366149] omap4iss omap4iss: ###ISP5 SYSCONFIG=0x00000021
[   96.366149] omap4iss omap4iss: ###ISP5 CTRL=0x0190c7f8
[   96.366149] omap4iss omap4iss: ###ISP5 IRQSTATUS(0)=0x00000000
[   96.366180] omap4iss omap4iss: ###ISP5 IRQENABLE_SET(0)=0x800c8001
[   96.366180] omap4iss omap4iss: ###ISP5 IRQENABLE_CLR(0)=0x800c8001
[   96.366180] omap4iss omap4iss: ------------------------------

-----------------

[   96.366943] omap4iss omap4iss: -------------CSI2 Register dump-------------
[   96.366943] omap4iss omap4iss: ###CSI2 SYSCONFIG=0x00001000
[   96.366943] omap4iss omap4iss: ###CSI2 SYSSTATUS=0x00000001
[   96.366973] omap4iss omap4iss: ###CSI2 IRQENABLE=0x00007b01
[   96.366973] omap4iss omap4iss: ###CSI2 IRQSTATUS=0x00000000
[   96.366973] omap4iss omap4iss: ###CSI2 CTRL=0x0029a811
[   96.367004] omap4iss omap4iss: ###CSI2 DBG_H=0x00000000
[   96.367004] omap4iss omap4iss: ###CSI2 COMPLEXIO_CFG=0x4a000321
[   96.367004] omap4iss omap4iss: ###CSI2 COMPLEXIO_IRQSTATUS=0x00000000
[   96.367034] omap4iss omap4iss: ###CSI2 SHORT_PACKET=0x00000000
[   96.367034] omap4iss omap4iss: ###CSI2 COMPLEXIO_IRQENABLE=0x07ffffff
[   96.367034] omap4iss omap4iss: ###CSI2 DBG_P=0x00000000
[   96.367065] omap4iss omap4iss: ###CSI2 TIMING=0x7fffe1ff
[   96.367065] omap4iss omap4iss: ###CSI2 CTX_CTRL1(0)=0x000100c9
[   96.367065] omap4iss omap4iss: ###CSI2 CTX_CTRL2(0)=0x0000012a
[   96.367095] omap4iss omap4iss: ###CSI2 CTX_DAT_OFST(0)=0x00000000
[   96.367095] omap4iss omap4iss: ###CSI2 CTX_PING_ADDR(0)=0x00000000
[   96.367095] omap4iss omap4iss: ###CSI2 CTX_PONG_ADDR(0)=0x00000000
[   96.367126] omap4iss omap4iss: ###CSI2 CTX_IRQENABLE(0)=0x00000002
[   96.367126] omap4iss omap4iss: ###CSI2 CTX_IRQSTATUS(0)=0x00000000
[   96.367126] omap4iss omap4iss: ###CSI2 CTX_CTRL3(0)=0x00000000

[   98.375671] omap4iss omap4iss: -------------ISS HL Register dump-------------
[   98.383239] omap4iss omap4iss: ###ISS HL_REVISION=0x40000103
[   98.389282] omap4iss omap4iss: ###ISS HL_SYSCONFIG=0x00000028
[   98.395385] omap4iss omap4iss: ###ISS HL_IRQSTATUS_5=0x00000000
[   98.401641] omap4iss omap4iss: ###ISS HL_IRQENABLE_5_SET=0x00000031

[   98.431610] omap4iss omap4iss: ###ISS HL_IRQENABLE_5_CLR=0x00000031
[   98.438262] omap4iss omap4iss: ###ISS CTRL=0x00000003
[   98.453063] omap4iss omap4iss: ###ISS CLKCTRL=0xf0000006
[   98.458709] omap4iss omap4iss: ###ISS CLKSTAT=0xf0000006
[   98.464324] omap4iss omap4iss: -----------------------------------------------

[OMAP4460]: McSPI in Slave mode with DMA

Vladik G. — Mon, 06 May 2013 05:45:22 GMT

Hello everyone!

I'm trying to launch McSPI in slave mode with DMA on OMAP4460 processor.
The kernel I use is based upon TI's kernel "UBUNTU: version 3.4.0-1489.22"
(commit d8a13c28e3ddc1f7cb098823b883dbc6a02bcb43).

The Linux target board is connected via SPI to an FPGA and FPGA transmits data to CPU.
When testing the entire setup with Linux functioning as SPI master
DMA works flawlessly and data being transmitted fine.
(Please don't suggest to leave it in master mode, this is impossible
for various reasons).

To facilitate the entire software design Linux behaves not as a real SPI slave
but as an "assisted" SPI slave: first McSPI is prepared to receive data
(spi_sync, etc), then a command is given to FPGA to start transmission.
What is important that clock is supplied by FPGA not by McSPI.
Transmission of the same data via CPU instead of DMA with Linux being SPI slave
also works although have natural shortcoming over DMA transmission.

Now the details: the setup utilizes channel 0 of SPI1. Most changes done
in spi-omap2-mcspi.c:

channel is put into slave mode by setting bit 2 of MCSPI_MODULCTRL register
(in omap2_mcspi_set_master_mode).
receive FIFO is being used for the transfers: set bit 28 of MCSPI_CHCONF0.
This works fine with CPU instead of DMA (in omap2_mcspi_setup_transfer).
forcing CS is disabled for slave mode (in omap2_mcspi_setup_transfer).

Running such transfer results in DMA stall: it does not transfer anything.
At the same time SPI shows that both FIFO and RxReg are full. Moreover,
bit RX1_FULL of MCSPI_IRQSTATUS is asserted and according to OMAP4460 TRM
"In DMA mode, the SPIm_DMA_RXx request is asserted on the same conditions as
the MCSPI_IRQSTATUS RXx_FULL flag."

This seems really weird as DMA read request is not asserted (or DMA ignores it).

The entire snapshot of SPI and DMA registers is shown below.
Any idea of what is missing to start DMA transfer in this situation?

Thanks,
Vladik

MCSPI_HL_HWINFO = 0x00000011 (@0x48098004)
MCSPI_XFERLEVEL = 0x00000300 (@0x4809817C)
MCSPI_SYSCONFIG = 0x0000001D (@0x48098110)
MCSPI_MODULCTRL = 0x00000005 (@0x48098128)
MCSPI_IRQSTATUS = 0x00000000 (@0x48098118)
MCSPI_WAKEUPENABLE = 0x00000001 (@0x48098120)
MCSPI_CHxCONF = 0x100197CC (@0x4809812C)
MCSPI_CHxSTAT = 0x00000020 (@0x48098130)
MCSPI_CHxCTRL = 0x00000000 (@0x48098134)

DMA4_CAPS_0 = 0x001C0000 (@0x4A056064)
DMA4_CAPS_2 = 0x000001FF (@0x4A05606C)
DMA4_CAPS_3 = 0x000000F3 (@0x4A056070)
DMA4_CAPS_4 = 0x00007FFE (@0x4A056074)
DMA4_GCR = 0x00010010 (@0x4A056078)
DMA4_CCRi = 0x01084084 (@0x4A056080)
DMA4_CLNK_CTRLi = 0x00000000 (@0x4A056084)
DMA4_CICRi = 0x00000922 (@0x4A056088)
DMA4_CSRi = 0x00000000 (@0x4A05608C)
DMA4_CSDPi = 0x00000001 (@0x4A056090)
DMA4_CENi = 0x0043DBFF (@0x4A056094)
DMA4_CFNi = 0x00000001 (@0x4A056098)
DMA4_CSSAi = 0x4809813C (@0x4A05609C)
DMA4_CDSAi = 0xAB300000 (@0x4A0560A0)
DMA4_CSEIi = 0x00000000 (@0x4A0560A4)
DMA4_CSFIi = 0x00000000 (@0x4A0560A8)
DMA4_CDEIi = 0x00000000 (@0x4A0560AC)
DMA4_CDFIi = 0x00000000 (@0x4A0560B0)
DMA4_CSACi = 0xB595E592 (@0x4A0560B4)
DMA4_CDACi = 0x00000000 (@0x4A0560B8)
DMA4_CCENi = 0x00000000 (@0x4A0560BC)
DMA4_CCFNi = 0x00000000 (@0x4A0560C0)
DMA4_COLORi = 0x00000000 (@0x4A0560C4)
DMA4_CDPi = 0x00000000 (@0x4A0560D0)
DMA4_CNDPi = 0x00000000 (@0x4A0560D4)
DMA4_CCDNi = 0x00000000 (@0x4A0560D8)

hook detection

chang shen — Thu, 02 May 2013 10:45:14 GMT

Hi,

My project is based on OMAP4430 and WinCE/WM6.5 OS. From the hook detection analog diagram in TWL6040 document, when the button on headset is pressed, it generates low/high impedance from COMPOUT, but I can't find any variables or registers related to COMPOUT to receive its value.

There are two registers HKCTL1 and HKCTL2, but they seems for control setting only.

How can I read the result of hook detection from COMPOUT?

Thanks,

Chang-Chih

Android 4.2.5 does not boot on Blaze Board

Prakash Divate — Tue, 21 May 2013 09:22:02 GMT

Hi,

I've been trying to bring up android 4.2.5 on Blaze board (4430) from SD card. As the kernel starts booting "untracked pid" keeps coming up on the screen continuously and i dont see anything coming up on the UI on the board except for the backgroud light. logcat shows that there is surfaceflinger error pertaining to framebuffer. Could anyone please guide me through this?

I have attached the entire boot log and logcat for your reference.

Thank You

Prakash

Looking for I2C multi-master driver for OMAP4460 running Linux 3.4.0

Tom McVeigh — Tue, 21 May 2013 14:43:18 GMT

Greetings,

I am interfacing an SMB battery charger to an OMAP4460 based system and suspect that the I2C driver is not multi-master compliant. While I can read the battery when attached directly to my I2C bus (tried 25kHz to 100Khz bus speed), when I place it in the charger which is also a Master, the data returned from the battery is all 1's. The manufacturer of the battery and the changer indicate that I must be able to support multi-master SMB transactions. While the OMAP appears capable, my investigations indicate that the Linux kernel driver has not implemented multi-master mode.

Can someone confirm that the I2C driver in Linux 3.4.0 is not multi-master? If so, is there a driver available for it?

I am using an OMAP4460 mobile processor. My platform is a third party System On Module. My operating system revision is constrained to 3.4.0 as that is the latest my vendor supports for this platform.

Thank you very much for your assistance,

Tom

MIPI DSI Low power Clk lane Voltage setting

wu william — Tue, 21 May 2013 07:45:39 GMT

Hi~

We meet a problem about that Clk lane Voltage haven't require MIPI SPEC (min 880mv ) , but only 850mv here.

Could we change voltage by modify dsi register??

thank you.

non-X11 OpenGL ES library

Keiji Nishida — Fri, 17 May 2013 08:35:09 GMT

I need non-X11 OpenGL libraries. I have 2 questions.

Firstly, Is it included in GLP package ?

Secondly, Is it built from SGX Driver Development Kit ?

I think maybe these libraries are not provided in open source community. (I had searched linaro and ubuntu-tiomap-dev.)

So, I think i should get GLP package or SGX DDK package under license.

If libraries aren't included, i will build it from SGX DDK package.

http://processors.wiki.ti.com/index.php/Graphics_SDK_Quick_installation_and_user_guide#make_command_line_options_details

In this page, it is built from SGX Driver Development Kit in OMAP3. Is it possible in OMAP4 ?

Can't set wallpaper for 1920x1200 dpi

Ping-Chu Hung — Tue, 13 Nov 2012 08:25:10 GMT

Hi,

My pandaboard outputs 1920x1200@30 from DPI correctly.

Setting's here: https://gist.github.com/3956747

When I set a live(dynamic) wallpaper, it works normally.

When I set a normal(static) wallpaper, it fails with black background (but app icons are normal).

And the logcat displays following message:

E/AndroidRuntime( 341): FATAL EXCEPTION: main
E/AndroidRuntime( 341): java.lang.RuntimeException: createWindowSurface failed EGL_BAD_ALLOC
E/AndroidRuntime( 341): at com.android.systemui.ImageWallpaper$DrawableEngine.initGL(ImageWallpaper.java:598)
E/AndroidRuntime( 341): at com.android.systemui.ImageWallpaper$DrawableEngine.drawWallpaperWithOpenGL(ImageWallpaper.java:396)
E/AndroidRuntime( 341): at com.android.systemui.ImageWallpaper$DrawableEngine.drawFrameLocked(ImageWallpaper.java:326)
E/AndroidRuntime( 341): at com.android.systemui.ImageWallpaper$DrawableEngine.onSurfaceChanged(ImageWallpaper.java:265)
E/AndroidRuntime( 341): at android.service.wallpaper.WallpaperService$Engine.updateSurface(WallpaperService.java:685)
E/AndroidRuntime( 341): at android.service.wallpaper.WallpaperService$Engine.attach(WallpaperService.java:772)
E/AndroidRuntime( 341): at android.service.wallpaper.WallpaperService$IWallpaperEngineWrapper.executeMessage(WallpaperService.java:1015)
E/AndroidRuntime( 341): at com.android.internal.os.HandlerCaller$MyHandler.handleMessage(HandlerCaller.java:61)
E/AndroidRuntime( 341): at android.os.Handler.dispatchMessage(Handler.java:99)
E/AndroidRuntime( 341): at android.os.Looper.loop(Looper.java:137)
E/AndroidRuntime( 341): at android.app.ActivityThread.main(ActivityThread.java:4746)
E/AndroidRuntime( 341): at java.lang.reflect.Method.invokeNative(Native Method)
E/AndroidRuntime( 341): at java.lang.reflect.Method.invoke(Method.java:511)
E/AndroidRuntime( 341): at com.android.internal.os.ZygoteInit$MethodAndArgsCaller.run(ZygoteInit.java:788)
E/AndroidRuntime( 341): at com.android.internal.os.ZygoteInit.main(ZygoteInit.java:555)
E/AndroidRuntime( 341): at dalvik.system.NativeStart.main(Native Method)
E/InputDispatcher( 272): channel '41f1d808 NotificationPanel (server)' ~ Channel is unrecoverably broken and will be disposed!

The caller tree is

InitGL() in ImageWallpaper.java

==> eglCreateWindowSurface() in EGLImpl.java

==> jni_eglCreateWindowSurface() in com_google_android_gles_jni_EGLImpl.cpp

==> eglCreateWindowSurface() in eglApi.cpp

And I can sure the error was happening in

EGLSurface surface = cnx->egl.eglCreateWindowSurface( iDpy, config, window, attrib_list);

But this function is in the GLES library and can't be traced.

Does anyone know how can I fix this problem?

USB communication for Pandaboard (minicom / gtkterm)

Hugh Tay — Tue, 14 May 2013 20:55:53 GMT

Dear readers,

I'm currently trying to build the FireFox OS for my Pandaboard ES, but unfortunately I'm stuck at the USB communication step, and I'm hoping that someone could help me out here.

Long story short, I'm unable to talk to my Pandaboard on [ gtkterm ] via USB and I can't figure out what sort of noob mistake I made.

---

My setup for the Pandaboard is here:

My output for [ lsusb ] and [ dmesg ] is here:

I'm pretty sure that the USB channel on my PC is working because the same steps allow me to talk to my TI AM335x board (similar to Beaglebone) even without the SD card.

My setup for the AM335x is here:

My output for [ lsusb ] and [ dmesg ] is here:

---

I would greatly appreciate any tips or suggestions that anyone would like to offer. =)

Cheers,

Hugh

Display resolution adjustment for OMAP4 based board

michelle villegas — Fri, 10 May 2013 15:52:18 GMT

Hi, is just that i am working with a Pandaboard ES, with Android 4.0 and kernel 3.0.8, and i'm using the parallel display option with an LVDS converter and a 14'' LCD (also a 15.6'' LCD), but the resolution is not the right one, so i modified the /drivers/video/omap2/displays/panel-generic-dpi.c and the max resolution that i could get was 1330x770 but is not the right one for the LCDs, i still have a black strip because the resolution is not being adjusted to the LCD, is there a way to change it in Android, for it to be adjusted complete to the LCD??? , because when i try a bigger resolution, the system UI stops working. i really need some help on this, thanks in advanced.

Incorrect MIPI DSI Video Mode Display on Panda Board

Scott Lin — Thu, 28 Feb 2013 09:36:43 GMT

Hi,

I am trying to set up a MIPI DSI video mode driver for a 720x1280 24-bit panel with the following timing requirements on the Panda board (OMAP4460).

Frame rate = 60Hz

PCLK = 72MHz

Vsync_width = 4 lines

Vback_porch = 4 lines

Vfront_porch = 4 lines

Hsync_width = 38 PCLKs

Hback_porch = 74 PCLKs

Hfront_porch = 96 PCLKs

All four data lanes are used for video transfer and the following is the omap_dss_device data structure used.

static struct omap_dss_device omap4_panda_dsi_device =
{
   .name = "dsi",
   .driver_name = "vid_mode_panel",
   .type = OMAP_DISPLAY_TYPE_DSI,
   .data = &dsi1_panel,
   .phy.dsi = {
       .clk_lane = 3,
       .clk_pol = 0,
       .data1_lane = 2,
       .data1_pol = 0,
       .data2_lane = 1,
       .data2_pol = 0,
       .data3_lane = 4,
       .data3_pol = 0,
       .data4_lane = 5,
       .data4_pol = 0,
       .type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
   },
   .clocks = {
       .dispc = {
           .channel = {
               .lck_div = 1,
               .pck_div = 2,
               .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
           },
           .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
       },
       .dsi = {
           .regn = 19,
           .regm = 213,
           .regm_dispc = 6,
           .regm_dsi = 6,
           .lp_clk_div = 7,
           .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
       },
   },
   .channel = OMAP_DSS_CHANNEL_LCD,
};

I am getting display on the panel with the driver but the display is not correct as shown in the picture below. A portion of the top half of the display is shown again on the bottom half, and the original top half is somewhat corrupted. Which settings/parameters may need to be adjusted in order to resolve this kind of display issue? The clock, dispc, and dsi settings from the driver are shown below. Thank you.

Scott

shell@android:/ # cat /d/omapdss/clk
- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
- DISPC -
dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
fck             143494692
- DISPC-CORE-CLK -
lck             143494692       lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck             143494692       lck div 1
pck             71747346        pck div 2
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck             42666666        lck div 4
pck             42666666        pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint            2021052         regn 19
CLKIN4DDR       860968152       regm 213
DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 143494692       regm_dispc 6    (on)
DSI_PLL_HSDIV_DSI (PLL1_CLK2)   143494692       regm_dsi 6      (on)
- DSI1 -
dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
DSI_FCLK        143494692
DDR_CLK         215242038
TxByteClkHS     53810509
LP_CLK          10249620

shell@android:/ # cat /d/omapdss/dispc
DISPC_REVISION                                     00000040
DISPC_SYSCONFIG                                    00002015
DISPC_SYSSTATUS                                    00000001
DISPC_IRQSTATUS                                    000100a2
DISPC_IRQENABLE                                    0012d640
DISPC_CONTROL                                      00018309
DISPC_CONFIG                                       00020004
DISPC_CAPABLE                                      00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD)          00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT)        00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD)            00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT)          00000000
DISPC_LINE_STATUS                                  0000044f
DISPC_LINE_NUMBER                                  00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD)               04905f25
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD)               00400403
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD)               00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD)               00010002
DISPC_GLOBAL_ALPHA                                 ffffffff
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT)             00000000
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD)               04ff02cf
DISPC_CONTROL2                                     00000000
DISPC_CONFIG2                                      00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2)         00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2)           00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2)              00000000
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2)              00000000
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2)              00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2)              00040001
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2)              00000000
DISPC_OVL_BA0(OMAP_DSS_GFX)                        7e000000
DISPC_OVL_BA1(OMAP_DSS_GFX)                        7e000000
DISPC_OVL_POSITION(OMAP_DSS_GFX)                   00000000
DISPC_OVL_SIZE(OMAP_DSS_GFX)                       04ff02cf
DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX)                 12000099
DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX)             04ff0130
DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX)           00000500
DISPC_OVL_ROW_INC(OMAP_DSS_GFX)                    00000041
DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX)                  00000001
DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX)                00000000
DISPC_OVL_TABLE_BA(OMAP_DSS_GFX)                   00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD)            00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD)            00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD)            00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD)             00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD)             00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD)             00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2)           00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2)           00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2)           00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2)            00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2)            00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2)            00000000
DISPC_OVL_PRELOAD(OMAP_DSS_GFX)                    000004ff
DISPC_OVL_BA0(o)                                   7c9d8000
DISPC_OVL_BA1(o)                                   7c9d8000
DISPC_OVL_POSITION(o)                              00000000
DISPC_OVL_SIZE(o)                                  04cf02cf
DISPC_OVL_ATTRIBUTES(o)                            16208018
DISPC_OVL_FIFO_THRESHOLD(o)                        07ff04c0
DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
DISPC_OVL_ROW_INC(o)                               00000041
DISPC_OVL_PIXEL_INC(o)                             00000001
DISPC_OVL_FIR(o)                                   04000400
DISPC_OVL_PICTURE_SIZE(o)                          04cf02cf
DISPC_OVL_ACCU0(o)                                 00000000
DISPC_OVL_ACCU1(o)                                 00000000
DISPC_OVL_FIR_COEF_H(o, i)                         264c26f4
DISPC_OVL_FIR_COEF_H(o, i)                         2f481ff2
DISPC_OVL_FIR_COEF_H(o, i)                         354916f0
DISPC_OVL_FIR_COEF_H(o, i)                         3b450ff0
DISPC_OVL_FIR_COEF_H(o, i)                         08404008
DISPC_OVL_FIR_COEF_H(o, i)                         0f453b01
DISPC_OVL_FIR_COEF_H(o, i)                         164935fc
DISPC_OVL_FIR_COEF_H(o, i)                         1f482ff7
DISPC_OVL_FIR_COEF_HV(o, i)                        264c26f4
DISPC_OVL_FIR_COEF_HV(o, i)                        2f481ff8
DISPC_OVL_FIR_COEF_HV(o, i)                        354916fc
DISPC_OVL_FIR_COEF_HV(o, i)                        3b450f01
DISPC_OVL_FIR_COEF_HV(o, i)                        084040f0
DISPC_OVL_FIR_COEF_HV(o, i)                        0f453bf0
DISPC_OVL_FIR_COEF_HV(o, i)                        164935f0
DISPC_OVL_FIR_COEF_HV(o, i)                        1f482ff3
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_FIR_COEF_V(o, i)                         0000f4f4
DISPC_OVL_FIR_COEF_V(o, i)                         0000f8f2
DISPC_OVL_FIR_COEF_V(o, i)                         0000fcf0
DISPC_OVL_FIR_COEF_V(o, i)                         000001f0
DISPC_OVL_FIR_COEF_V(o, i)                         0000f008
DISPC_OVL_FIR_COEF_V(o, i)                         0000f001
DISPC_OVL_FIR_COEF_V(o, i)                         0000f0fc
DISPC_OVL_FIR_COEF_V(o, i)                         0000f3f7
DISPC_OVL_BA0_UV(o)                                00000000
DISPC_OVL_BA1_UV(o)                                00000000
DISPC_OVL_FIR2(o)                                  04000400
DISPC_OVL_ACCU2_0(o)                               00000000
DISPC_OVL_ACCU2_1(o)                               00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_ATTRIBUTES2(o)                           00000000
DISPC_OVL_PRELOAD(o)                               000007ff
DISPC_OVL_BA0(o)                                   7cd4e000
DISPC_OVL_BA1(o)                                   7cd4e000
DISPC_OVL_POSITION(o)                              04d00000
DISPC_OVL_SIZE(o)                                  002f02cf
DISPC_OVL_ATTRIBUTES(o)                            0a20840c
DISPC_OVL_FIFO_THRESHOLD(o)                        07ff0358
DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
DISPC_OVL_ROW_INC(o)                               00000021
DISPC_OVL_PIXEL_INC(o)                             00000001
DISPC_OVL_FIR(o)                                   04000400
DISPC_OVL_PICTURE_SIZE(o)                          002f02cf
DISPC_OVL_ACCU0(o)                                 00000000
DISPC_OVL_ACCU1(o)                                 00000000
DISPC_OVL_FIR_COEF_H(o, i)                         264c26f4
DISPC_OVL_FIR_COEF_H(o, i)                         2f481ff2
DISPC_OVL_FIR_COEF_H(o, i)                         354916f0
DISPC_OVL_FIR_COEF_H(o, i)                         3b450ff0
DISPC_OVL_FIR_COEF_H(o, i)                         08404008
DISPC_OVL_FIR_COEF_H(o, i)                         0f453b01
DISPC_OVL_FIR_COEF_H(o, i)                         164935fc
DISPC_OVL_FIR_COEF_H(o, i)                         1f482ff7
DISPC_OVL_FIR_COEF_HV(o, i)                        264c26f4
DISPC_OVL_FIR_COEF_HV(o, i)                        2f481ff8
DISPC_OVL_FIR_COEF_HV(o, i)                        354916fc
DISPC_OVL_FIR_COEF_HV(o, i)                        3b450f01
DISPC_OVL_FIR_COEF_HV(o, i)                        084040f0
DISPC_OVL_FIR_COEF_HV(o, i)                        0f453bf0
DISPC_OVL_FIR_COEF_HV(o, i)                        164935f0
DISPC_OVL_FIR_COEF_HV(o, i)                        1f482ff3
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_FIR_COEF_V(o, i)                         0000f4f4
DISPC_OVL_FIR_COEF_V(o, i)                         0000f8f2
DISPC_OVL_FIR_COEF_V(o, i)                         0000fcf0
DISPC_OVL_FIR_COEF_V(o, i)                         000001f0
DISPC_OVL_FIR_COEF_V(o, i)                         0000f008
DISPC_OVL_FIR_COEF_V(o, i)                         0000f001
DISPC_OVL_FIR_COEF_V(o, i)                         0000f0fc
DISPC_OVL_FIR_COEF_V(o, i)                         0000f3f7
DISPC_OVL_BA0_UV(o)                                00000000
DISPC_OVL_BA1_UV(o)                                00000000
DISPC_OVL_FIR2(o)                                  04000400
DISPC_OVL_ACCU2_0(o)                               00000000
DISPC_OVL_ACCU2_1(o)                               00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_ATTRIBUTES2(o)                           00000000
DISPC_OVL_PRELOAD(o)                               000007ff
DISPC_OVL_BA0(o)                                   7d0e6000
DISPC_OVL_BA1(o)                                   7d0e6000
DISPC_OVL_POSITION(o)                              04d00000
DISPC_OVL_SIZE(o)                                  002f02cf
DISPC_OVL_ATTRIBUTES(o)                            0a20840c
DISPC_OVL_FIFO_THRESHOLD(o)                        07ff0358
DISPC_OVL_FIFO_SIZE_STATUS(o)                      00000800
DISPC_OVL_ROW_INC(o)                               00000021
DISPC_OVL_PIXEL_INC(o)                             00000001
DISPC_OVL_FIR(o)                                   04000400
DISPC_OVL_PICTURE_SIZE(o)                          002f02cf
DISPC_OVL_ACCU0(o)                                 00000000
DISPC_OVL_ACCU1(o)                                 00000000
DISPC_OVL_FIR_COEF_H(o, i)                         264c26f4
DISPC_OVL_FIR_COEF_H(o, i)                         2f481ff2
DISPC_OVL_FIR_COEF_H(o, i)                         354916f0
DISPC_OVL_FIR_COEF_H(o, i)                         3b450ff0
DISPC_OVL_FIR_COEF_H(o, i)                         08404008
DISPC_OVL_FIR_COEF_H(o, i)                         0f453b01
DISPC_OVL_FIR_COEF_H(o, i)                         164935fc
DISPC_OVL_FIR_COEF_H(o, i)                         1f482ff7
DISPC_OVL_FIR_COEF_HV(o, i)                        264c26f4
DISPC_OVL_FIR_COEF_HV(o, i)                        2f481ff8
DISPC_OVL_FIR_COEF_HV(o, i)                        354916fc
DISPC_OVL_FIR_COEF_HV(o, i)                        3b450f01
DISPC_OVL_FIR_COEF_HV(o, i)                        084040f0
DISPC_OVL_FIR_COEF_HV(o, i)                        0f453bf0
DISPC_OVL_FIR_COEF_HV(o, i)                        164935f0
DISPC_OVL_FIR_COEF_HV(o, i)                        1f482ff3
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_CONV_COEF(o, i)                          00000000
DISPC_OVL_FIR_COEF_V(o, i)                         0000f4f4
DISPC_OVL_FIR_COEF_V(o, i)                         0000f8f2
DISPC_OVL_FIR_COEF_V(o, i)                         0000fcf0
DISPC_OVL_FIR_COEF_V(o, i)                         000001f0
DISPC_OVL_FIR_COEF_V(o, i)                         0000f008
DISPC_OVL_FIR_COEF_V(o, i)                         0000f001
DISPC_OVL_FIR_COEF_V(o, i)                         0000f0fc
DISPC_OVL_FIR_COEF_V(o, i)                         0000f3f7
DISPC_OVL_BA0_UV(o)                                00000000
DISPC_OVL_BA1_UV(o)                                00000000
DISPC_OVL_FIR2(o)                                  04000400
DISPC_OVL_ACCU2_0(o)                               00000000
DISPC_OVL_ACCU2_1(o)                               00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_H2(o, i)                        00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_HV2(o, i)                       00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_FIR_COEF_V2(o, i)                        00000000
DISPC_OVL_ATTRIBUTES2(o)                           00000000
DISPC_OVL_PRELOAD(o)                               000007ff

shell@android:/ # cat /d/omapdss/dsi1_regs
DSI_REVISION                        00000030
DSI_SYSCONFIG                       00000015
DSI_SYSSTATUS                       00000001
DSI_IRQSTATUS                       00000000
DSI_IRQENABLE                       0015c000
DSI_CTRL                            00eae299
DSI_COMPLEXIO_CFG1                  6a054123
DSI_COMPLEXIO_IRQ_STATUS            00000000
DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
DSI_CLK_CTRL                        a0344007
DSI_TIMING1                         ffff7fff
DSI_TIMING2                         ffff7fff
DSI_VM_TIMING1                      00047052
DSI_VM_TIMING2                      04040404
DSI_VM_TIMING3                      02b80500
DSI_CLK_TIMING                      00001a10
DSI_TX_FIFO_VC_SIZE                 13121110
DSI_RX_FIFO_VC_SIZE                 13121110
DSI_COMPLEXIO_CFG2                  00030000
DSI_RX_FIFO_VC_FULLNESS             00000000
DSI_VM_TIMING4                      00487296
DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
DSI_VM_TIMING5                      0082df3b
DSI_VM_TIMING6                      7a6731d1
DSI_VM_TIMING7                      0012000f
DSI_STOPCLK_TIMING                  00000080
DSI_VC_CTRL(0)                      20808f91
DSI_VC_TE(0)                        00000000
DSI_VC_LONG_PACKET_HEADER(0)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
DSI_VC_SHORT_PACKET_HEADER(0)       00000000
DSI_VC_IRQSTATUS(0)                 00000004
DSI_VC_IRQENABLE(0)                 000000db
DSI_VC_CTRL(1)                      20808f81
DSI_VC_TE(1)                        00000000
DSI_VC_LONG_PACKET_HEADER(1)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
DSI_VC_SHORT_PACKET_HEADER(1)       00000000
DSI_VC_IRQSTATUS(1)                 00000004
DSI_VC_IRQENABLE(1)                 000000db
DSI_VC_CTRL(2)                      20808d81
DSI_VC_TE(2)                        00000000
DSI_VC_LONG_PACKET_HEADER(2)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
DSI_VC_SHORT_PACKET_HEADER(2)       00000000
DSI_VC_IRQSTATUS(2)                 00000000
DSI_VC_IRQENABLE(2)                 000000db
DSI_VC_CTRL(3)                      20808d81
DSI_VC_TE(3)                        00000000
DSI_VC_LONG_PACKET_HEADER(3)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
DSI_VC_SHORT_PACKET_HEADER(3)       00000000
DSI_VC_IRQSTATUS(3)                 00000000
DSI_VC_IRQENABLE(3)                 000000db
DSI_DSIPHY_CFG0                     12281220
DSI_DSIPHY_CFG1                     42060f38
DSI_DSIPHY_CFG2                     b800000e
DSI_DSIPHY_CFG5                     ff000000
DSI_PLL_CONTROL                     00000000
DSI_PLL_STATUS                      00000383
DSI_PLL_GO                          00000000
DSI_PLL_CONFIGURATION1              14a1aa25
DSI_PLL_CONFIGURATION2              00656008

Write a word in u-boot

willy ho — Fri, 17 May 2013 09:53:31 GMT

I'm trying to control MSP430 by I2C in u-boot

I have a problem with I2C driver "omap24xx_i2c.c"

It's only provide i2c_write_byte function, but I want to write a word

Is there has any new driver provide i2c_write_word function

Thanks

DSP transforms on the Cortex A9

Hac Le — Thu, 16 May 2013 02:09:39 GMT

Can I implement DSP transforms (Fast Fourier Transform - FFT for example) on the Cortex A9 ? Is there a DSP library to support this?

OMAP4460 can not boot from MMC2

tuan duong — Sat, 05 Jan 2013 15:46:55 GMT

Hi all,

I use the http://omappedia.com/wiki/4AI.1.4_OMAP4_Icecream_Sandwich_Panda_Notes for my 4460 panda board. Everything is good. But I want to boot panda board from MMC2. So I use J3 expansion connector that according to the block:

I also configure SYSBOOT pin of OMAP to boot according to order of peripheral : USB-UART-MMC1-MMC2. I user usb4boot (http://pandaboard.org/content/usb-downloader-and-usb-second-stage-bootloader-omap4) to boot uboot into omap4460. When I’m in uboot, I use “mmc_init 1” command to start SD card. But the initialization is fail and I cann’t read or write the SD card use uboot command.

Help me!

Thank you for your help and reply.

Best regards!

SW solution for Acoustic Echo Cancellation and Noise suppression on OMAP4430+TWL6040

chang shen — Fri, 08 Mar 2013 01:48:16 GMT

Hi,

I have a new project based on OMAP4 platform and Windows Mobile 6.5, it seems no echo and noise cancellation on OMAP4430+TWL6040, I have found the AEC/AER SW on TI's website : http://software-dl.ti.com/sdoemb/sdoemb_registered_sw/aer/latest/index_FDS.html

then I downloaded aer_gcarmv7a_obj_16_0_0_1_Win32.exe from the site, but this SW on the request site only supported OS options for installers are Linux and Windows for the PC.

Does someone have any ideas how to install AEC/AER SW on WM6.5?

If not, is there any way to implement echo and noise cancellation on OMAP4430+TWL6040?

Thanks,

Chang-Chih

Hardware accelerated video performance

Carol Pinto — Mon, 29 Apr 2013 06:14:58 GMT

Hi,

I'm using ducati codecs and SGX based videosink on a non-debian based distribution. I followed the steps provided at http://e2e.ti.com/support/omap/f/849/p/249986/875729.aspx#875729 .

The video performance doesn't seem to be great. The framerate is lesser than the actual framerate. Are the gst ducati plugins and the codecs provided at https://launchpad.net/~tiomap-dev/+archive/release/ optimized enough for a decent performance? Am i missing out on something?

Thanks in advance,

Carol

Qt and Video playback in Omap4

Carol Pinto — Tue, 09 Apr 2013 05:54:05 GMT

Hi,

I am developing a QT application to browse and play the videos in an USB device on OMAP4 platform. I built the QT application and I was able to run it. But in order to play the video in omap4, I need to start X (for DCE authentication) and export DISPLAY variable (for hardware accelerated codecs and pvrvideosink). When this happens, Iam not able to see the QT screen since it dumps into the linux framebuffer by default. How do I proceed ?

Thanks in advance,

Carol

OMAP4470's SYS_PWR_REQ can not be pulled down by OMAP after suspend

Scott Cheng — Wed, 15 May 2013 03:56:47 GMT

We met a suspend issue on OMAP4470. Our BSP code base is 4AJ.2.2

When we press the power button to enter suspend mode, we found that the SYS_PWR_REQ signal did not be pulled down by OMAP.

We got the debug message "Successfully put all powerdomains to target state" after resumed the device.

We also checked power domain's last pwr state, we found that CORE, MPU, L3INIT, L4PER are in retention mode and others are in off mode.

It looks like that all power domains enter low power state.

Why the SYS_PWR_REQ does not be pulled down by OMAP?

Does the OMAP4470 still not enter off mode?

Could you provide some information about this issue?

Thank you.

LCD graphics,

Manjula.M — Tue, 14 May 2013 05:30:45 GMT

We have a code for displaying of graphics on LCD which is there on OMAPL138 EVM kit. I didn't understand the code completely, can anyone explain about the logic behind the code and can we display the text on it, if so how can we do that? How to create serial communication between OMAPL138 EVM kit and UI board?

Thanks,

Regards,

Manjula.

4AJ.2.5 Release on the OMAP4 GP device

vinod krishnankutty — Sun, 12 May 2013 08:14:56 GMT

Hi All,

I am trying to get Android 4AJ.2.5 release from omapedia working on the Blaze with the OMAP 4470 ES1.0. Using the 0005-wakeupgen-avoid-crash-in-early-boot patch from http://e2e.ti.com/support/omap/f/849/p/253953/888544.aspx#888544 i am able to get the kernel booted.

However the backlight turns on but i do not see anything on the display. After bootup I see the following error continuously displayed on the serial console.

[ 12.645294] PVR_K:(Error): BridgedDispatchKM: Initialisation failed. Driver unusable. [0, ]
[ 13.155151] PVR_K:(Error): BridgedDispatchKM: Initialisation failed. Driver unusable. [0, ]

The complete boot log is attached for reference, looking forward for your inputs.

Thanks,

Vinod

How to enable the wifi on blaze Tablet (OMAP4)

mukesh thakur1 — Mon, 13 May 2013 11:54:42 GMT

How to enable the wifi on the blaze tablet,kernel version is 3.0.8.I have flashed the new kernel image but when i am trying to reboot it ,showing

ERROR could not get firmware: -2

ERROR firmware boot failed despite 3 retries

unloaded

Please help me out to fix it.

Thanks in advanced

Regards

Mukesh