Panda Dithering for 18bit LCD

From my understanding, OMAP4 is not designed to support 18bit LCD, like in OMAP3. So the Pin mapping needs to changed as per the fig 17 in Page 19 of the SN75LVDS83B Data sheet (Rev B). Basically the LSB 2bits should be ignored or not be connected. For improved image quality, the OMAP4 should dither the 24-bit output pixel down to18-bit per pixel. Normally in OMAP3, the 2 MSB bits will be ignored for 18bit mode.

This is not right. I misunderstood the issue. OMAP4 can work in 18bit mode.

Hi,

What exactly do you mean by artigraft?

Display Controller(DISPC) of OMAP4 generates 24 bits by default, but your understanding is right about you can configure the pin mapping if you want to use a 18 bit panel(bridge). There are different ways to do this mapping.

Since your panel is an active panel, you should set TFT. You can do that by setting 0x01 to DISPC_CONTROLo[3] STNTFT bit.

According to TRM, by doing so, you need to configure two submodules:

• Spatial/temporal dithering
• Multiple cycle output format (TDM)

For dithering, you need to configure basically two things:

Configure number of frames:
DISPC_CONTROLo[31:30] SPATIALTEMPORALDITHERINGFRAMES bit field.

Enable spatial/temporal dithering logic:
DISPC_CONTROLo[7] STDITHERENABLE bit to 0x1.

And for TDM (here is where you configure the mapping), you need to configure the following:

Configure cycles:
DISPC_CONTROLo TDMCYCLEFORMAT bit
DISPC_DATAo_CYCLE1
DISPC_DATAo_CYCLE2
DISPC_DATAo_CYCLE3

Configure data bus:
DIPSC_CONTROLo[9:8] TFTDATALINES bit field.

Hope this helps,

Thanks Jorge. DISPC is set to LCD2, TFT, STNTFT and Dithering mode are selected. TFTDATALINES are set to 18. But No improvement. With this setting, what I was trying to achieve is, with-out changing the current DSS pin mapping (which was similar to OMAP3) and correcting it thru TDM Cycle setting. But it is not working for me.

Any other pointers? Is it possible to handle this with-out changing the pin mapping?

Trying understand the RGB666_PACKED mode, command mode and video mode. I am not sure, whether it will help to overcome the pin mapping issue with-out hardware modification, Just trying :)

Hello Midson,  

 May  i ask you some question about lcd ?

Yes. Please.

Dear all,

we tried to activate dithering (by setting the registers mentioned above) but could not see any improvement. The TDM settings are not fully clear to us. With TDM being activated there is no picture at all. Option 4 results in an image with completely strange colors.

• Settings Option 1 (no TDM, spatial only):

devmem 0x48041238 32 0x389

• Settings Option 2 (no TDM, spatial and temporal over 4 frames)

devmem 0x48041238 32 0x80000389

• Settings Option 3 (trying TDM):

devmem 0x48041238 32 0x81100389
devmem 0x480413C0 32 0x8
devmem 0x480413C4 32 0x8
devmem 0x480413C8 32 0x2

• Settings Option 4 (dithering with 18Bit output):

devmem 0x48041238 32 0x289

We applied two different hardware designs. Both use the SN75LVDS83B for connecting the OMAP4460 with the 18 Bit TFT display.

• HW-Option 1 applies the design for connecting all data wires (24 Bit), cp. Figure 15 ("24-Bit Color Host to 24-Bit LCD Panel Application").
• HW-Option 2 applies the design for connecting only the required wires (18 Bit), cp. Figure 18 ("24-Bit Color Host to 18-Bit Color LCD Panel Display Application").

Actually, there is no visible difference.

Is there anything we are missing? Could anyone provide a working configuration, e.g. define the specific registers?

Hello Michael,

It seems your configurations are correct.

The dithering logic can process the pixels over one frame, two frames, or four frames. The number of frames is selected by setting the DISPC_CONTROLo[31:30] SPATIALTEMPORALDITHERINGFRAMES bit field. In the case of a single frame, only spatial processing is applied, and in multiple frames, spatial and temporal processing are applied to the pixels. The spatial/temporal dithering logic is enabled by setting the DISPC_CONTROLo[7] STDITHERENABLE bit to 0x1.

Select Spatial/Temporal number of frames  - DISPC_CONTROLo[31:30]  SPATIALTEMPORALDITHERINGFRAMES

Enable Spatial/Temporal dithering - DISPC_CONTROLo[7] STDITHERENABLE

I suggest you to follow the settings described in section 10.2.5.1.2.5.5 Subsequence - Configure the LCD Panel Timings and Parameters of OMAP4 TRM.

For dithering settings you can see in /kernel/android-3.4/drivers/gpu/drm/ drm_crtc.c in your software release.

Best regards,

Yanko

Dear Yanko,

many thanks for your immediate reply! We followed the configuration sequence and did not experience any difference.

Actually we are still puzzling whether we have a HW design issue or just a problem with the settings. Let me summarize the current behaviour:

• The display (18Bit) works fine. We would like to activate dithering at this stage to have better quality.
• HW-Design: please see my previous post -
  Figure 15 (24Bit, Format 2) AND Figure 18 (18 Bit) tested. Same results.
  cp. http://www.ti.com/lit/ds/symlink/sn75lvds83b.pdf
• DISPC_CONTROLo [9:8] TFTDATALINES = 0x3 (24-bit output):
  All colors are displayed correctly. Switching on/off dithering does not show any difference at all.
• DISPC_CONTROLo [9:8] TFTDATALINES = 0x2 (18-bit output):
  Colors are wrong. However switching dithering on/off and changing dithering configuration (spatial vs. temporal) shows a clear effect!

Is the physical mapping in our HW design wrong? Is Figure 16 the one we should follow?

Is it possible to define the data wire mapping by changing register values?

Many thanks for your support & Best Regards

Michael

Hello Michael,

Is the physical mapping in our HW design wrong?

- Could you provide more information about your HW design?

Had TI made a hardware review on your board?

Is Figure 16 the one we should follow?

- Do you have in mind figure in TRM - Figure 10-16. LCD Pixel Data Color16 Active Matrix?

I suggest you to check following registers -

Active matrix timing configuration 1
– DISPC_POL_FREQo[17] ONOFF bit = 0
– DISPC_POL_FREQo[16] RF bit = 0
The HSYNC and VSYNC signals are driven on the opposite edge of PCLK from the pixel data.

Is it possible to define the data wire mapping by changing register values?

- Yes, you can use pad registers defined in Control module. See section 19.4.8.3 Pad Multiplexing Register Fields
in OMAP4 TRM.

Best regards,

Yanko

Dear Yanko and all,

thanks for your help!

We have tried changing the timing configuration (DISPC_POL_FREQ...) without any success.

All the Figures I have mentioned in my post can be found in the SN75LVDS83B documentation.
(Download link: http://www.ti.com/lit/ds/symlink/sn75lvds83b.pdf)

Our original hardware design corresponds to Figure 15 (24 Bit, Format 2). However, we have temporarily adopted Figure 18 and Figure 16 for testing purposes.

I hope you don't mind repeating the results from my earlier post:

1. HW-Design according to Figure 16:

• All colours are wrong independently from the register settings.

2. HW-Design according to Figure 15 (Format 2) and 18:

• 2a) DISPC_CONTROLo [9:8] TFTDATALINES = 0x3 (24-bit output):
  Colors are correct. Quality is ok but not optimal in gradients. Switching on/off dithering does not show any difference at all (neither spatial nor temporal).
• 2b) DISPC_CONTROLo [9:8] TFTDATALINES = 0x2 (18-bit output):
  Colors are wrong. However switching dithering on/off and changing dithering configuration show a clear effect (both spatial and temporal)!

Do you have any clue what is happening here? We assumed the best and correct HW design would be Figure 18 (because of Note B in the caption).

Have a nice weekend & Many thanks

Michael