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OMAP 4 Forum
Issues with MCSPI1 MultiChannels
I am using a PandaBoard for development but this issue is more related to the MCSPI1 port. I have both a SPI flash and a FPGA connected to MCSPI1. CS0 is used for the SPI Flash and no chip select is needed for the FPGA since the SPI is only used to configure the FPGA at start up.
I would like to configure Channel 0 for the SPI flash and Channel 1 for the FPGA. During start up, I need to configure the FPGA first. No matter what I do, I cannot get Channel 1 to work. Since I don't need a chip select for the FPGA, if I use Channel 0, then I can configure the FPGA.
Here is one strange thing that I saw when I was stepping through the code using Channel 1. Only Channel 1 is enabled, Channel 0 is disabled. The STAT registers for Channel 0 is 0x0 and for Channel 1 is 0x2 which is what I expected. I write the first value into the TX register. The STAT register for Channel 1 becomes 0 but Channel 0 becomes a 0x7. I don't know how the STAT register for Channel 0 can change since the channel was not enabled.
Any idea why this is happening?
The McSPI port has some mode to work when you "manually" change the channel enabled and another automatic when you make a write to the channel it will change the CS, this mode is used for saving time or cycle process.
For more information I recommend you to read the information about McSPI in the TRM of the OMAP version in your Pandaboard.
I am not "manually" changing the channels. I started with Channel 1. I looked through the TRM, Version K and I don't see anything relevant.
However, are you telling me that I have to start transferring data with Channel 0 before I can proceed to use Channel 1? I cannot simply start with another channel other than Channel 0?
No, I am not saying that you have to start with Channel 0. What I say is that if you have the module configured to use two channels and have it in automatic it will change from channel 1 to channel 0 once it finish the transfer. Then if you make a transfer to Channel 0 and it finish it will change to Channel 1 and so on. That is for automatic mode.
For manual you can make any write as you want to the channel and will never change.
According to Section 18.104.22.168.2 Master Transmit-and-Receive Mode (Full Duplex), the arbiter will search in the rotation only for enabled channels. Since I only enabled Channel 1, that doesn't explain how Channel 0 STAT register is suddenly went from 0x0 to 0x7 when I only wrote to Channel 1 TX register..
I also have the SINGLE bit in MODULCTRL register set to 1. Only one channel will be used in master mode.
I haven't tried it yet but I will interface first with Channel 0 to the SPI flash before I try to interface with Channel 1 to the FPGA. See if that makes a different since there is a arbiter involved.
Yes, but I think the channel needs to start from channel 0 and be subsequent.
Did you try using channel 0 instead of 1?, what happen?
Channel 0 works fine at all times. When I have time, I will go back and use Channel 0 and then Channel 1 to see what happens.
It would be nice if the TRM have a paragraph stating use of channels must start with Channel 0.
Channel 1 does work if Channel 0 is first configured and a transfer is done. At that point, configure Channel 1 and Channel 1 can then be used.
So, don't configure Channel 1 until Channel 0 is used because it will not work.
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