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OMAP4460 McBSP1 in master mode.

EZAndy
Prodigy 20 points

I have two questions.

1) I want to put McBSP1 in master mode. When doing that I want to SRG to run off McBSP1_ICLK. What is the register setting for that? and what is the clock rate of McBSP1_ICLK?

2) The machine driver calls snd_soc_set_sysclk(X, X, 64*param_rate(params), X, X). The interface is running at 8 kHz. Why is the multiple of 64 there? If my set up is 

   FS = 8 kHz, 1 channel and word length of 16 bit what should this value be?

  • 0
    Prodigy 20 points

    I have found the solution to Q1. and set up the registers such that the SRG is driven by CLKS which in turn is driven by MCBSPi_FCLK. I still need an answer for Q2 though. Thanks folks, all help appreciated.

  • 0 in reply to EZAndy
    TI__Mastermind 29520 points

    Hello,

    McBSP module in OMAP4 supports two groups standard sample rates 48KHz and 44.1KHz.

    Based on required sample rate it is recommended the clock signal to be configured as multiple of 96KHz (48KHz x 2).

    For example - McBSP clock is provided by the system clock and is set to 12.288MHz (48KHz × 256), where 256 is the value for Sample Rate Generator Clock Divider, which should be set in the MCBSPLP_SRGR1_REG[7:0] CLKGDIV bit field.

    The FS - frame-sync signal defines the frame length, each frame consists of a fixed number of words.

    You can check [12] bit in register MCBSPLP_SRGR2_REG[12]FSGM Sample Rate Generator Transmit Frame-Synchronization.

    Best regards,

    Yanko











  • 0 in reply to EZAndy
    Prodigy 170 points

    Hello EzAndy,


    I'm in the process of modifying the code to configure the MCBSP1 master mode. From the info above, it was not very clear.  It will be great if you could point to what changes went into the code to achieve this and source file you touched 

    FYI - i'm using the 3.4 pandaboard  kernel from SVT.

    Also i had one more question, Is there any muxing change required for this to work. Plan is to connect an external codec in slave mode( McBSP1 provides the clk).

    Is this something which can be achieved?


    Thanks,

    Rich