This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OMAP4460 4AJ.1.1 with 2GB RAM

Other Parts Discussed in Thread: 4460

  Hi,

We already porting 4AJ.1.1 on 1GB device and it is working fine.

And we got a new HW with 2GB RAM and it's work with 1GB code.

So I change some code in u-boot and x-loader

x-loader: sdram_elpida.c

__raw_writel(0x80740300, DMM_BASE + DMM_LISA_MAP_3);
__raw_writel(0x80720100, MA_BASE + DMM_LISA_MAP_0);
__raw_writel(0xFF020100, MA_BASE + DMM_LISA_MAP_1);
__raw_writel(0x00000000, MA_BASE + DMM_LISA_MAP_2);
__raw_writel(0x80740300, MA_BASE + DMM_LISA_MAP_3);

u-boot:   cmd_bootm.c

 strcat (bootarg, " mem=2040M ");

bootarg shows:

console=ttyO2,115200n8 androidboot.console=ttyO2 init=/init vram=64M omapfb.vram=0:32M consoleblank=0 mem=2040M 

 

and remove ducati-m3.bin but still has problem with following message from kernel

[ 92.757507] init: cannot execve('/system/bin/mediaserver'): Accessing a corrupted shared library
[ 92.766845] Unable to handle kernel paging request at virtual address df8d1647
[ 97.839416] Unable to handle kernel paging request at virtual address df8d1647
[ 102.912506] Unable to handle kernel paging request at virtual address df8d1647
[ 107.986267] Unable to handle kernel paging request at virtual address df8d1647
[ 113.060668] Unable to handle kernel paging request at virtual address df8d1647

 

 

 

 

 

 

 

 

 

 

  • Hello Willy,

    2-GB SDRAM address ranges over two chip-selects (CSs) (1GB per CS) (configurable with the
    dynamic memory manager (DMM) module.

    To support 2GB RAM it is needed the bit-field  DMM_LISA_MAP_i[22:20] SYS_SIZE to be written with 0x7 corresponding to 2GB section - DMM system section size for view mapping

    For more information about Memory maping, refer to section 15.2.3.5.1 DMM Concepts in OMAP4460 TRM.

    Best regards,

    Yanko

  • I am trying to incorporate 2 GB RAM support into my OMAP4460 Linux BSP. We do have 512 MB, 1 GB with 2 CS, and 1 GB with 1 CS RAM solutions working.

    I am working on getting this up in running in barebox. The issue I am having seems due to accessing above 1 GB of RAM. The current problem is an error when booting barebox after doing a malloc.


    I am trying to verify that my LISA_MAP registers are set accordingly. For the previous RAM versions the settings were as follows:

    (arch/arm/mach-omap/omap4_generic.c)

           /* Both EMIFs 128 byte interleaved */
            writel(0x80640300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);

            writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
            writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);

            if (rev >= OMAP4460_ES1_0) {
                    writel(0x80640300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);

                    writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2);
                    writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3);
            }

    When adding 2 GB, I changed to the following:

           /* Both EMIFs 128 byte interleaved */
            writel(0x80740300, OMAP44XX_DMM_BASE + DMM_LISA_MAP_0);

            writel(0x00000000, OMAP44XX_DMM_BASE + DMM_LISA_MAP_2);
            writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);

            if (rev >= OMAP4460_ES1_0) {
                    writel(0x80740300, OMAP44XX_MA_BASE + DMM_LISA_MAP_0);

                    writel(0x00000000, OMAP44XX_MA_BASE + DMM_LISA_MAP_2);
                    writel(0xFF020100, OMAP44XX_MA_BASE + DMM_LISA_MAP_3);
            }

    I have been referring to the Section pointed out in TRM but am not sure I understand how the LISA_MAP registers should be set. Does any one have any pointers?

  • I have done some additional testing. The system boots with max 1.9GB RAM setup in the board file. Anything higher will result in a kernel crash. Any one else seeing a similar issue?

  • Hello Serah,

    2-GB SDRAM address ranges over two chip-selects (CSs) (1GB per CS) (configurable with the dynamic memory manager (DMM) module.

    These chip-selects can be programmed to 64, 128, 256, 512, and 1024MB. Interleaving occurs at 128-MB granularity.
    EMIF1-CS1 and EMIF2-CS1 are disabled at reset. Their base address is programmable to achieve a continuous address space with the respective CS0, regardless of the address range programmed. EMIF1-CS1 is disabled if EMIF1-CS0 memory density is set to 2048MB (2GB) when interleaving is disabled, or if EMIF1-CS0 + EMIF2-CS0 memory density are set to 1024MB (1GB) when interleaving is enabled.

    Best regards,

    Yanko

  • Hi Yanko,

    Thank you for the information.

    Where do you program 64, 128, 256, 512, and 1024 MB for the chip-selects?

    I have tried disabling interleaving and am seeing the same behavior. Is there any limitations from the processor for using the full 2 GB of RAM? It is interesting that it works when I subtract 16MB from the total RAM.

    This does not work:

    omap_add_ram0(0x80000000);

    This does work:

    omap_add_ram0(0x7F000000);

  • I think I have found an explanation.

    16MiB are not accessible because they are used as specified in LISA_MAP_3:

    writel(0xFF020100, OMAP44XX_DMM_BASE + DMM_LISA_MAP_3);

    From this I can gather the following:

    * SYS_SIZE = 0x0 --> 16MiB

    * SDRC_ADDRSPC = 0x2 --> From Table 15.3.4.1.1 L3 Interface in the TRM the MAddrSpace 0x2 corresponds to Reserved section that is not visible to the MA port.

    So the 16MB can not be used because this is grabbed from requests to addresses with the top 8-bits 0xFF and are used for reserved functionality. The max RAM you can get is then 2GB - 16MB. Does that sound right? Anyone else see this limitation in 2 GB RAM implementations?

  • Hello Serah,

    Each EMIF controller supports two independent chip selects (CS). In total, up to 2GB of LPDDR2 memory can be addressed.

    The default interleaving configuration for OMAP4430 ES2.0+, OMAP4460, and OMAP4470 is for a 1GB LPDDR2. If a different LPDDR2 size is used, the DMM_LISA_MAP_3[22:20], which is the SYS_SIZE, should be configured to match the LPDDR2 size. SYS_SIZE = 0x5 indicates a 512MB section, 0x6 a 1GB section, and 0x7 a 2GB section.

    The Blaze board file is /arch/arm/mach-omap2/board-4430sdp.c, and the Blaze Tablet board file is /arch/arm/mach-omap2/board-44xx-tablet.c. OMAP4430 and 4460 Blaze and Blaze Tablet SOMs are built with a 2Gb LPDDR2 connected to CS0 and CS1 of both EMIF1 and EMIF2, which gives a total of 8Gb (1GB) LPDDR2.

    To support 2GB RAM with OMAP4 you must apply some modifications in following files:
    x-loader/cpu/omap4/ sdram.c - I suggest you to see errata bug i614 in OMAP4430 ERRATA - http://focus.ti.com/pdfs/wtbu/swpz009D.pdf

    u-boot/cpu/omap4/ omap4.c

    Take a look on this function:

    /*
     * This function finds the SDRAM size available in the system
     * based on DMM section configurations
     * This is needed because the size of memory installed may be
     * different on different versions of the board
     */
    u32 sdram_size(void)
    {
        u32 section, i, total_size = 0, size, addr;
        u32 sdrc_addrspc;
        u32 sdrc_map;

        for (i = 0; i < 4; i++) {
            section    = __raw_readl(DMM_LISA_MAP + i*4);
            addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
            sdrc_addrspc = (section & DMM_LISA_MAP_SDRC_ADDRSPC_MASK) >>
                DMM_LISA_MAP_SDRC_ADDRSPC_SHIFT;
            sdrc_map = (section & DMM_LISA_MAP_SDRC_MAP_MASK) >>
                DMM_LISA_MAP_SDRC_MAP_SHIFT;

            /* Take into account only mapped sections */
            if (0 == sdrc_map)
                continue;

            /* Handle only DMM sections which define physical SDRAM
             * configuration */
            if (DMM_SDRC_ADDRSPC_SDRAM != sdrc_addrspc)
                continue;

            /* update SDRAM size */
            size    = ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
                    DMM_LISA_MAP_SYS_SIZE_SHIFT);
            size    = 1 << size;
            size    *= SZ_16M;
            total_size += size;

        }
        return total_size;
    }

    kernel/android-3.4/arch/arm/mach-omap2/ board-4430sdp.c

    kernel/android-3.4/arch/arm/mach-omap2/ board-44xx-tablet.c

    kernel/android-3.4/arch/arm/mach-omap2/ omap4_ion.c

    Best regards,

    Yanko