OMAP 4430 GPMC Burst mode

Hello Christian,

The GPMC in OMAP4430 supports asynchronous, synchronous, and page mode (only available in non-muxed mode) burst NOR flash devices.

Only linear burst transactions are supported

#Q1: Is there anything else I need to configure to get the burst mode working? Does the clock speed matter?
I expect the chip select to stay low through all the reads/writes, but currently is toggling back and forth with each read/write.

Address Decoder and Chip-Select Configuration

Only power-of-two-length precise bursts 2 x 32, 4 x 32, 8 x 32 or 16 x 32 with the burst base address aligned on the
total burst size are supported (this limitation applies to incrementing bursts only).

It is recommended to program the ATTACHEDDEVICEPAGELENGTH field (GPMC_CONFIG1_i[24:23]) according to the effective attached device page length and to enable WRAPBURST bit (GPMC_CONFIG1_i[31]) if the attached device supports wrapping burst.

Similarly, during a multiple-access cycle (for example, asynchronous read page mode), the effective
access time is a logical AND combination of PAGEBURSTACCESSTIME timing completion and the wait-
deasserted state. Wait-monitoring pipelining is also applicable to multiple accesses (access within a
page).

Error Handling:

ERRORTIMEOUT: A time-out mechanism prevents the system from hanging. The start value of the 9-
bit time-out counter is defined in the GPMC_TIMEOUT_CONTROL register and enabled with the
GPMC_TIMEOUT_CONTROL[0] TIMEOUTENABLE bit. When enabled, the counter starts at start-
cycle time until it reaches 0 and data is not responded to from memory, then a time-out error occurs.
When data are sent from memory, this counter is reset to its start value. With multiple accesses
(asynchronous page mode or synchronous burst mode), the counter is reset to its start value for each
data access within the burst.

To ensure a correct external clock cycle, the following rules must be applied:
•
(RDCYCLETIME CLKACTIVATIONTIME) must be a multiple of (GPMCFCLKDIVIDER +
1).
•
The PAGEBURSTACCESSTIME value must be a multiple of (GPMCFCLKDIVIDER +
1).

The GPMC module uses L3_ICLK2 as functional clock (GPMC_GFCLK) from PRCM. For more information about this signal refer to PRCM chapter.

GPMC clock configuration:
The gpmc_clk is generated by the GPMC from the internal GPMC_FCLK clock. The source of the GPMC_FCLK.
The gpmc_clk is configured via the GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER field (for i = 0 to 7)
The GPMC_SYSCONFIG[0] AUTOIDLE - This bit allows a local power optimization inside the module, by gating the GPMC_FCLK clock upon the internal activity.

See the functions in /arch/arm/mach-omap2/ gpmc.c

/* TODO: Add support for gpmc_fck to clock framework and use it */
unsigned long gpmc_get_fclk_period(void)
{
    unsigned long rate = clk_get_rate(gpmc_l3_clk);

    if (rate == 0) {
        printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
        return 0;
    }

    rate /= 1000;
    rate = 1000000000 / rate;    /* In picoseconds */

    return rate;
}

Refer to section 15.4.5.6.1 GPMC Timing Parameters Formulas in OMAP4430 TRM for proper calculating of the GPMC timing bit fields values

I suggest you to refer to this example http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x,_AM35x,_and_AM-DM37x_GPMC_registers

#Q2: I have read on other posts, that others have configured their DMA to get the burst mode working, is this a necessary step to get the burst mode?

The GPMC interface provides one interrupt and one DMA request line, for specific event control.

The use of DMA module with GPMC, depends on your specific use case.

You must use the DMA with GPMC in:

- Prefetch and Write-Posting Engine

- FIFO Control in Prefetch Mode
- FIFO Control in Write-Posting Mode

It is recommended to program the ATTACHEDDEVICEPAGELENGTH field (GPMC_CONFIG1_i[24:23])
according to the effective attached device page length and to enable WRAPBURST bit (GPMC_CONFIG1_i[31]) if the attached device supports wrapping burst.

You can enable or disable DMA mode by the function in /arch/arm/mach-omap2/ gpmc.c

/**
 * gpmc_prefetch_enable - configures and starts prefetch transfer
 * @cs: cs (chip select) number
 * @fifo_th: fifo threshold to be used for read/ write
 * @dma_mode: dma mode enable (1) or disable (0)
 * @u32_count: number of bytes to be transferred
 * @is_write: prefetch read(0) or write post(1) mode
 */
int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                unsigned int u32_count, int is_write)
{

    if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
        pr_err("gpmc: fifo threshold is not supported\n");
        return -1;
    } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
        /* Set the amount of bytes to be prefetched */
        gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);

        /* Set dma/mpu mode, the prefetch read / post write and
         * enable the engine. Set which cs is has requested for.
         */
        gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
                    PREFETCH_FIFOTHRESHOLD(fifo_th) |
                    ENABLE_PREFETCH |
                    (dma_mode << DMA_MPU_MODE) |
                    (0x1 & is_write)));

        /*  Start the prefetch engine */
        gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
    } else {
        return -EBUSY;
    }

    return 0;
}

Best regards,

Yanko

Yanko,

Thank you very much for taking time to respond my question. 

Im still working on getting the right timing parameters. I still have several high level questions regarding the burst mode:

1) Does the GPMC need to use the DMA in order to get burst mode working, or is that an extra that we can use to get faster speeds?

2) Currently another team is working on the FPGA, it is connected on our board but not set up. Can I keep working on the OMAP and expect to see to see some of the signals (i.e nCS, clks, nADV, nOE, etc.) working correctly? I would like to have the GPMC working so when the FPGA team is ready we can integrate everything. 

3) Does the GPMC/OMAP expect certain signals (handshaking) coming from the FPGA in order to get the GPMC working (ie. during a read or write)?

Thanks,

Christian Archilla