OMAP4460 eMMC Flash and SDMMC Interface

Hi Yordan,

Thanks for the reply. I have some specific questions related to this.

The link you shared http://www.micron.com/products/managed-nand/e-mmc#fullPart&225=3

These are eMMC from Micron which have 16GB Density, Now as I refer the Datasheet of this part "MTFC16GJDDQ-4M IT" has 8BIT datalines and compared to that GPMC of OMAP4460 has two modes

i) Multiplexed GPMC (26bit Address - 16bit Data)

ii) Nonmultiplexed GPMC (10bit Address - 16bit Data)

How can it be interfaced? Do I have to leave Address lines, and Higher 8Bit data lines?

The Micron shows the following Image: As we see right side, it just requires the data, command line and clock.

I have referred to DARTBoard schematics, they have just shown the connectors in which they have used the address lines (Schematics Page 3, DART J3 Connector).

Can you please make it clear?

Thanks in Advance

Regards, 

Rushi Gajjar

Hi Yordan, 

Its a current phase when I am curious to know the Interfacing of eMMC and OMAP4460.

I am using SDMMC2 port.

I have chosen, MTFC8GLDDQ-4M IT to interface with OMAP4460. The TRM of OMAP4460 says [on page: 3412] this connection.

My NAND memory device has these pins {DATA[0:7], RST_n, CMD and CLK}

I have kept

DATA[0:7] to

gpmc_ad[7]  -> D7
gpmc_ad[6]  -> D6
gpmc_ad[5]  -> D5
gpmc_ad[4}  -> D4
gpmc_ad[3]  -> D3
gpmc_ad[2]  -> D2
gpmc_ad[1] ->  D1
gpmc_ad[0]  -> D0

gpmc_clk -> CLK

1 ) I want to know that, which are the suitable pins for RST_n and CMD for this eMMC on OMAP4460?

2) You told in last post that "When using eMMC you should connect it to SDMMC2 (not GPMC)"  So are GPMC and SDMMC2 different? , In High Tier environment example in TRM also shows that GPMC backs the SDMMC2 and also in TRM they are used interchangeably e.g. "SDMMC2 or GPMC I/O cell pads" 

PS:

In brief about RST_n and CMD

RST_n: 

Reset: The RST_n signal is used by the host for resetting the device, moving the device to the preidle
state. By default, the RST_n signal is temporarily disabled in the device.

CMD:

Command: This signal is a bidirectional command channel used for command and response transfers. Commands are sent from the MMC host to the device, and responses are sent from the device to the host.

Hi Rushi Gajjar,

Sorry for the delayed response.

GPMC & eMMC are two different controllers in OMAP4460 SoC, they have different signalling and different guidelines for interfacing with memory chips. 

I see that you've decided to use GPMC. So besides the data pins gpmc_ad[7:0] and gpmc_clk pin you need to connect also the gpmc_noe (Output enable); gpmc_nwe (Write enable) and gpmc_nwp (Write protect) pads to the appropriate memory pads (on your MTFC8GLDDQ-4M IT eMMC).

In the schematics I have (blaze schematics) there are no CMD & RST signals. I don't have the data sheet of your eMMC, so If CMD & RST are mandatory to be connected and it is just a matter of driving the buses  low and high, you could program gpios to do it.

On the other hand the MMC controller has a dedicated sdmmci_cmd pin for CMD.

Best Regards,

Yordan