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Question about power scripts configuration (type and type2 configuration)

Raj Kumar8
Prodigy 30 points

Hi,

I am working on OMAP. In the PMIC chip, there are power scripts (e.g. in our case High frequency oscillator clk is coming from PMIC).  I want to understand more about .type and .type2 initialization for resources. I have gone through also TRM of PMIC chip which it programs to registers.

e.g., This is sample code:

static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
{ .resource = RES_VDD1, .devgroup = -1,
.type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
.remap_sleep = RES_STATE_OFF
},

I want to understand the .type and .type2 fields? How can we choose these fields while configuration? Another question is "is it mandatory for all OMAP family processors to configure these scripts?"

Regards,

Raj

  • 0
    TI__Guru**** 161600 points

    Hi Raj,

    The following article should shed some light on the powerscripts for OMAP4:
    http://www.omappedia.org/wiki/TWL4030_power_scripts

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 30 points

    Hi Yordan,

    I have few questions more.

    1)  In OMAP, since DPS/SLM are there, Does it means Device will auto transition to power off state if it is idle means there is no software supervision required?

    2) I think by default OMAP3/4 is going into retention state during suspend to RAM and resume perfectly. During suspend to RAM, why does it not go to power off state? Do you think that enabling the power scripts mandatory for going to power off state and resume will clean?

    3) I went to this link you sent, but in linux kernel there is DEVGRP_NULL (macro having value 0) is defined, when we broadcast message with DEVGRP_NULL, will it broadcast message to all groups (P1/P2/P3)?

    Thanks,

    Raj

  • 0 in reply to Raj Kumar8
    TI__Guru**** 161600 points

    Hi Raj,

    When DPS/SLM are used, the device auto transitions to low-power state, which is not necessarily OFF state (See Figure 3-9. Power Domain Transitions).

    In RETENTION state the voltages to the device are lowered to their minimum value to retain only the logic build with RFFs, while all DFF logic is lost. Not all registers have context registers (their values are not saved in SAR RAM) and they cannot recover their logic when device goes into OFF state; plus it is not guaranteed that RAM data will be recovered after off state.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 30 points

    Hi Yordan,

    Thanks for answers. Few more things:

    1) I am aware that OMAP auto transitions to low power state. But I was working on a project where I saw auto transitioning of domains through pmdbg/count. In my project IVA2 was not required, it was always on while kernel booting (TIDSP bridge driver disabled). Till suspend to RAM, it did not transition to low power state and this is sure no software is using that. It always remain on. Is there specific reason for this or missing some register configuration?

    2) Is DPS or SLM enabling require some register configuration or is it always enabled?

    Thanks,

    Raj

  • 0 in reply to Raj Kumar8
    TI__Guru**** 161600 points

    Hi Raj,

    DPS & SLM are not managed by sw (register configurations) if supported, they're always running on the background.

    The reason for IVA to be always on is because kernel keeps it that way. By default PM_IVAHD_PWRSTCTRL[1:0]POWERSTATE is set to0x3 (ON State); CM_IVAHD_IVAHD_CLKCTRL[1:0]MODULEMODE is set to 0x1 and CM_IVAHD_SL2_CLKCTRL[1:0]MODULEMODE is set to 0x1 in linux kernels, which keeps the IVA in ON state.

    If you'd like you could modify those registers to turn IVA to OFF state, that is set POWERSTATE=0x0 and set the IVAHD & SL2 MODULEMODE=0x0. This sw change should disable the IVA module and reduce your power consumption.

    Best Regards,
    Yordan