I am working on OMAP4430(panda board) for graphics application and trying to use the EMIF performance counters to measure the DDR bandwidth. The registers I used are EMIF_PERF_CNT_1, EMIF_PERF_CNT_2,EMIF_PERF_CNT_TIM, and EMIF_PERF_CNT_TIM. Looks there are two ways (described below) to measure the bandwidth based on the TRM, but they DO NOT agree with each other. Can you please help explain it? The two ways I think of are following. In addition, what is the relationship between EMIF clock, EMIF_L3_ICLK, EMIF_FCLK, and DDR_CLK?
1. Get the counter total read and counter total write (CNTR_CFG=2 and 3 respectively), and multiply them by 8 (burst length) and then by 4 (32 bit DDR data bus).
2. Get the count number of EMIF clock for tranferring data (CNTR_CFG=10, or 0x0A), and multiply it by 16 (because of the 128 bit L3 system bus).
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