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J5Eco - Problem with HW-De-Interlacing

Datis Danesh
Prodigy 100 points

We are seeing sporadic observations of a 'frozen video image' by disconnecting and connecting the video signal constantly over few hours of testing using a relay.

Findings:
- The PRI_MV_OUT channel (related to DEI) seems to be stuck in the BUSY state, and the associated VPDMA list (LIST4) is also busy.
- No DEI error interrupt is asserted. 
- register dump attached.

 

 

We don't reset the VIP while capturing video, so Advisory 1.1.58 shouldn't apply.
For Advisory 1.1.60, we do set the maximum width and height on the capture side; do we need something similar on DEI?

Potentially the maximum values should have some effect on some silicon revisions (as we are not able to reproduce the issue on EVM board). Is there some information about particular revs that could explain this behavior, or some logging we could add?

The firmware revision is shown in the register dump:

    VPDMA_PID               4D000288  SCHEME                            1         FUNC                              0D00  RTL                               0

                                          MAJOR                             2         VPDMA_LOAD_COMPLETE               1     VPDMA_ACCESS_TYPE                 0

                                          MINOR                             8

 

 

(Note that except for those containing "D" these fields are all decimals, as in TI's register dumper--but every other register uses hex values.)

 

We are using QNX 6.5.0 SP1 and screen package #523. 

  • 0
    TI__Guru**** 161600 points

    Hi,

    Datis Danesh said:
    Is there some information about particular revs that could explain this behavior, or some logging we could add?

    I am not aware of such difference between J5Eco silicon revisions.

    I am additionally digging inside design specs (and will contact IP owners) regarding your issue.

    Unfortunately I am not familiar with the QNX OS and cannot reproduce your problem, only pointers from hw perspective can be given.

    Another concern is that this device is NDA and its architecture cannot be discussed in a public forum. Could you please ask your local FAE to initiate internal discussion?

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 100 points

    Hi Yordan,

    Do you have any updates?

    You could contact our FAE (Stephan Haas) who is synced with this issue, if you cannot post your analysis here.

    Thanks,
    Datis

  • 0 in reply to Datis Danesh
    TI__Guru**** 161600 points

    Hi Datis,

    Yes we are discussing this internally.

    I am comparing the register dump you provided with HDVPSS design spec registers description, but I haven't finished it yet, so far I cannot see erroneous configuration, that might explain your issue.

    Stephan is in CC of the discussion.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Guru**** 399120 points

    Are you sure List 4 is is stuck? We have not seen M2M operation getting stuck unless list itself is corrupted or invalid. Also can you please sure that the sizes and formats configured in modules being used in the path and in the list are matching?

     

    In any case, can you write 0xDEAD0004 to the offset 0x4810d000, readback the value from the same offset and share the value? It may give some clue as to why list is stuck.

     

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 100 points

    Yes, we see LIST4 is busy:

    VPDMA_LIST_STAT_SYNC          00110000  LIST7_BUSY                        0         LIST6_BUSY          0     LIST5_BUSY                        0

                                              LIST4_BUSY                        1         LIST3_BUSY                        0     LIST2_BUSY                        0

                                              LIST1_BUSY                        0         LIST0_BUSY                        1     SYNC_LISTS7                       0

                                              SYNC_LISTS6                       0         SYNC_LISTS5                       0     SYNC_LISTS4                       0

                                              SYNC_LISTS3                       0         SYNC_LISTS2                       0     SYNC_LISTS1                       0

                                              SYNC_LISTS0                       0

     

     

    Here is the value and command used:

    # out32 0x4810d000 0xDEAD0004

    # in32 0x4810d000

    4810d000 : 0000000f

     

     

     

    Also attached please find the VPDMA register values from the base: 0x48100000.  

     

     

    Thanks,
    Datis