ds90ub925q I2S configuration

Hello Sandesh,

I suggest you check the power and clock configuration of McASP2 module.

Check the clock configuration for McAP2 module by registers:

CM_L4PER2_MCASP2_CLKCTRL
CM_L4PER2_CLKSTCTRL
CM_L4PER2_MCASP2_CLKCTRL

See the file with recommended clock configuration for McASP2 - 6786.McASP2_clk_conf.txt

McASP2 module belongs to L4PER power domain, check the state of this PD by the register -
PM_L4PER_PWRSTCTRL[1:0] POWERSTATE - 0x3: ON State

To enable I2S configuration for McASP2 module follow the sequence described in TRM: 24.6.5.1.2.3 Main Sequence – MCASP Global Initialization for TDM -Transmission - This is used for I2S (2-slot TDM) and other TDM-based audio protocols transmission.

You must mandatory configure the following registers in McASP2 module:

0x4846 406C - MCASP_RXFMCTL[15:7] RMOD 0x2: 2-slot TDM mode( I2S receive mode)
0x4846 40AC - MCASP_TXFMCTL[15:7] XMOD - 0x2: 2-slot TDM mode (I2S transmit mode)

Synchronous transmit and receive operations are allowed only in the MCASP TDM (I2S) mode (i.e. when MCASP_TXDITCTL[0] DITEN=0b0).

Note:

The MCASP does NOT transmit in "I2S format" on serializer 0, while transmitting "Left Justified" on serializer 1. Likewise, the receiver section of the MCASP only supports one data format at a time, and this format applies to all receiving serializers.

See the configuration for MCASP in sound/soc/davinci/davinci-mcasp.c

Did you configure the Control module PAD registers?

Configure these register to enable McASP2 module on the device's balls:

CTRL_CORE_PAD_MCASP2_ACLKX

CTRL_CORE_PAD_MCASP2_FSX
CTRL_CORE_PAD_MCASP2_ACLKR
CTRL_CORE_PAD_MCASP2_FSR
CTRL_CORE_PAD_MCASP2_AXR0 to 7

Best regards,

Yanko

Thanks Yanko,

I configured as follows in device tree on basis of your inputs.

in dra7.dtsi:

mcasp2: mcasp@48464000 {
compatible = "ti,dra7-mcasp-audio";
reg = <0x48464000 0x2000>; /*Address length*/
interrupts = <0 149 0x4>; /* AXEVT */
interrupt-names = "tx";
ti,hwmods = "mcasp2";
op-mode = <0>; /* I2S mode*/
tdm-slots = <2>; /* slots for TDM operation*/
num-serializer = <16>;
serial-dir = <0 1 0 0
0 0 0 0
0 0 0 0
0 0 0 0>; /* 0:INACTIVE, 1:TX, 2:RX */
ti,tx-inactive-mode = <2>; /* 0: Hi-Z, 2: Low, 3: High */
};

mcasp2_pins: pinmux_mcasp2_pins {
pinctrl-single,pins = <
0x30C 0x00080000 /*MCASP2_AXR2 OUTPUT */
0x2F4 0x00000000 /*MCASP2_ACLKX OUTPUT */
0x2F8 0x00080000 /*MCASP2_FSX OUTPUT */
>;
};

we not using MCASP2_AXR0 pin, so no need to configuration.

static struct omap_hwmod_dma_info dra7xx_mcasp2_sdma_reqs[] = {
{ .name = "49", .dma_req = 48 + DRA7XX_DMA_REQ_START },
{ .name = "50", .dma_req = 49 + DRA7XX_DMA_REQ_START },
{ .dma_req = -1 }
};

/* mcasp2 */
static struct omap_hwmod dra7xx_mcasp2_hwmod = {
.name = "mcasp2",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp2_ahclkr_mux",
.sdma_reqs = dra7xx_mcasp2_sdma_reqs,
.flags = HWMOD_SWSUP_SIDLE,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};

but we fail to create pcm interface to "aplay -l : no interfaces". 

please guide along with above configration, i need to configure any more changes?

thanks in advance.

Sandesh D

Hello Sandesh,

What is your board with DRA7xx?
Do you use DRA7xx EVM board by Texas Instruments or you use custom designed board?

If you use DRA7xx EVM board, you must apply your modifications in board-support/linux/arch/arm/boot/dts/ dra7-evm.dts

arch/arm/mach-omap2/cclock7xx_data.c

arch/arm/mach-omap2/omap_hwmod_7xx_data.c

See pins configuration in dra7xx-evm.dts:

radio_pins: pinmux_radio_pins {
        pinctrl-single,pins = <
            0x02F4     0x40000    /* MCASP2_ACLKX: MODE0 */
            0x02F8     0xc0000    /* MCASP2_AFSX: MODE0 */
            0x0304     0x40000    /* MCASP2_AXR0: MODE0 */
            0x0308     0x40000    /* MCASP2_AXR1: MODE0 */
            0x030C     0xc0000    /* MCASP2_AXR2: MODE0 */
            0x0310     0xc0000    /* MCASP2_AXR3: MODE0 */
            0x0314     0x40000    /* MCASP2_AXR4: MODE0 */
            0x0318     0x40000    /* MCASP2_AXR5: MODE0 */
            0x031c     0x40000    /* MCASP2_AXR6: MODE0 */
            0x0320     0x40000    /* MCASP2_AXR7: MODE0 */
            0x0334     0x70004    /* I2C4_SDA: MODE4 */
            0x0338     0x70004    /* I2C4_SCL: MODE4 */
            0x02A0     0x5000e    /* GPIO6_20: MODE14 */
        >;
    };

aplay is an ALSA command and you must check your ALSA configuration. For this purpose use the site - http://alsa.opensrc.org/TroubleShooting

NOTE: to use MCASP modules in DRA7xx device you must configure the register CM_L4PER2_CLKSTCTRL[1:0] CLKTRCTRL  - 0x2: SW_WKUP: Start a software forced wake-up transition on the domain.

Best regards,

Yanko

we using TI DRA7xx customized device , where we use MCASP2 pins configured to I2S of 925 Serializer, even we configured the other MCASP(3 and 4) lines for other audio interfaces, but with other configurations we are able to create interfaces, but fails for MCASP2.

Hope there is no special CLKTRCTRL - 0x2 configuration for MCASP2 interface.?

I confirmed the register values from sysfs entry(cat /sys/kernel/debug/..../pins) and pin configuration is fine.

Yanko,

Thanks for your points while configration and now we are able to create I2S interface and able to get ACLK and WS values properly(confirmed via CRO), but still we not able to get data.

MCASP_XRSRCTLn showing 0x19 , which explains as follows:

-----------------------------------------------------------------------------------------------------------------------------------------

4 XRDY Transmit buffer ready bit. XRDY indicates the current transmit buffer R 0
state. Always reads 0 when programmed as a receiver or as inactive. If
SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when
XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty
transmitter. XRDY remains set until XSRCLR is forced to 0, data is
written to the corresponding transmit buffer, or SRMOD bit is changed to
receive (2h) or inactive (0).
Read 0x0: The transmit buffer (MCASP_TXBUFn) contains data.
Read 0x1: The transmit buffer (MCASP_TXBUFn) is empty and needs to
be written before the start of the next time slot or a transmit underrun
occurs.

-------------------------------------------------------------------------------------------------------

The TX buffer is empty and there is no data is filling, we configured DMA and other configrations but still not able to get the data in buffer.

Please suggest me where i need to double check the value.

Hi Sandesh,

I am glad to hear that! :)

Best regards,

Yanko