Not able get the proper data from Reziser

Hi Gajanan,

Since your data path is VP->IPIPEIF->ISIF->IPIPEIF-IPIPE->BL, can you confirm that configuration of IPIPEIF input source selection is IPIPEIF_CFG1[15:14] INPSRC1=0x0 & IPIPEIF_CFG1[3:2] INPSRC2=0x0 (?); this corresponds to the case shown in Figure 8-129. ISS ISP IPIPEIF INPSRC1 = 0 and INPSRC2 = 0 Data Path.

Having the above image pipe, this means that input data (YUV4:2:2)  for RSZ is coming from IPIPE. In this case, when you don't need to resize the image you should configure RSZ in Bypass mode, not pass through.

See clarification bellow Figure 8-177. ISS ISP RSZ Typical Module Integration: High-Level Summary:
"The data coming from the IPIPE module can be RAW or YUV4:2:2 data. Eventually, YUV4:2:0 data can be sent through this path, but the data must be sent in two passes. Because the RSZ module can rescale only YUV4:2:2 data, the RSZ module must be configured in pass-through mode when RAW data is received on VP 1. It is possible to bypass the resizer engine if YUV4:2:2 data is sent but rescaling is not needed (bypass mode)."

I think this could be the cause of your timeout error.

Best Regards,

Yordan

Hi Yordan,

  Thanks a lot for your quick reply.

Yes, As you said "IPIPEIF_CFG1[15:14] INPSRC1=0x0 & IPIPEIF_CFG1[3:2] INPSRC2=0x0" is confirmed and it is with zero only.

Just to localize the issue I remove the IPIPE from the pipeline and made some changes in resizser to read the data from IPIPE-IF. Now the path becomes as....

"SENSOR -> VP -> IPIPEIF -> ISIF -> IFIPEIF  -> RSZ -> BL -> SDRAM"

Here we are expecting some data at SDRAM location, But the behaviour is same as first fame with zeros and timeout for multiple frame dump.

In this path I have tried in both Bypass mode and pass through mode, but the behaviour is same.

Here I am using media control path as...

./media-ctl -r -l '"OMAP4 ISS CSI2a":1 -> "OMAP4 ISS ISP IPIPEIF":0 [1]','"OMAP4 ISS ISP IPIPEIF":2 -> "OMAP4 ISS ISP resizer":0 [1]','"OMAP4 ISS ISP resizer":1 -> "OMAP4 ISS ISP resizer a output":0 [1]'

Please refer the below register dumps for better clarity.

RSZ_SRC_FMT0 is 0x3
RSZ_SRC_MODE is 0x0
RZA_MODE is 0x0
RSZ_SRC_VPS is 0x0
RSZ_SRC_HPS is 0x0
RSZ_SRC_VSZ is 0x437
RSZ_SRC_HSZ is 0x77f
RZA_I_VPS is 0x0
RZA_I_HPS is 0x0
RZA_O_VSZ is 0x437
RZA_O_HSZ is 0x77f
RZA_V_DIF is 0x100
RZA_H_DIF is 0x100
RZA_SDR_Y_PTR_S is 0x0
RZA_SDR_Y_PTR_E is 0x437
RZA_SDR_Y_OFT is 0xf00
RZA_420 is 0x0
RZA_SDR_C_PTR_S is 0x0
RZA_SDR_C_PTR_E is 0x0
RZA_SDR_C_OFT is 0x0

###IPIPEIF CFG1=0x00000000
###IPIPEIF CFG2=0x00000000
###ISIF SYNCEN=0x00000000
###ISIF CADU=0x00000000
###ISIF CADL=0x00000000
###ISIF MODESET=0x00000200
###ISIF CCOLP=0x000000e4
###ISIF SPH=0x00000000
###ISIF LNH=0x0000077f
###ISIF LNV=0x00000437
###ISIF VDINT0=0x00000437
###ISIF HSIZE=0x00001078
###ISIF CCDCFG=0x00000000
###ISIF CGAMMAWD=0x00000008
###ISP5 SYSCONFIG=0x00000021
###ISP5 CTRL=0x0190dff8
###ISP5 IRQSTATUS(0)=0x00000000
###ISP5 IRQENABLE_SET(0)=0x824c8201
###ISP5 IRQENABLE_CLR(0)=0x824c8201

Regards,

Gajanan Ambi

Hi Gajanan,

Here is what comes to my mind, at first glance of your register dump:

1. Check settings of RSZ_SRC_FMT1

   - bit[1]IN420 should be set to 0x0  //YUV4:2:2 is input

   - bit[0]RAW = 0x0 //Flipping preserves YCbCr format

2. Have you done any configurations in RSZ_IN_FIFO_CTRL ?
    I recommend setting bit field[28:16]THRLD_LOW = bit field[12:0]THRLD_HIGH = 0x0 //the rsz_stall_input is
                                                                                                                                                             //not asserted.

3. Try changing the IPIPEIF_CFG2[7:0] settings, according to your input data format (see description of these bits in OMAP5 TRM)

I'll continue digging in ISS setting options...

Best Regards,

Yordan

Hi Yordan,

  I did experiment with your suggestions, But no result as of now.