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GPMC Clock no Activity

Other Parts Discussed in Thread: SYSCONFIG

I'm trying to configure the GPMC clock to free-run after GPMC reset, but I'm not seeing any activity on the output pin (J20-35). There are many posts about this issue, but I'm curious if a continuous GMPC clock (non-gating) is supported in sync/non-multiplexed mode. In addition, I'm struggling to figure out why I can't see GPMC clock activity (at pin) during write operations. I can see the chip select and write enable, but no clock. I'm probing from the main expansion header, so there is no hardware interface connected to the GPMC.
 
The following CM registers show that the dependent clocks are active, which implies GPMC_FCLK is active:
 
1. CM_L3MAIN2_CLKSTCTRL = 0x103 ( RUNNING | HW_AUTO )

2. CM_L3MAIN2_L3_MAIN_2_CLKCTRL = 0x103 ( RUNNING | HW_AUTO )

3. CM_L3MAIN2_GPMC_CLKCTRL = 0x1 ( FUNCTIONAL | HW_AUTO )

The pad configuration is:

4. PAD_GPMC_CTRL = 0x104 ( PAD_MODE4 | PAD_PULL_DISABLE | PAD_PULL_DOWN | PAD_CELL_PWR_ON | PAD_INPUT | PAD_WAKEUP_DISABLE )

I successfully reset the GPMC, and then configure the GPMC_SYSCONFIG register again:

5. GPMC_SYSCONFIG = 0x8 ( FREE_RUN | NO_IDLE )

I then configure the CS0 in 16-bit synchronous non-multiplexed mode (NAND), and write to the base address continuously. Any ideas?

  • Hello Michael,

    gpmc_clk - Clock generated for the external memory or device.

    This output signal is also used as retiming input (the INPUTENABLE bit in the corresponding pad configuration register must be set to 1).

    GPMC is actually not usable directly as we don't have the GPMC_NOE_NRE signal available, and some external logic shall be needed.

    CONTROL_CORE_PAD0_UART2_RTS_PAD1_UART2_CTS[18:16] 0x4: Select gpmc_noe_nre

    Could you check the register:

    CONTROL_CORE_PAD0_C2C_CLKIN0_PAD1_C2C_CLKIN1[18:16] C2C_CLKIN1_MUXMODE - 0x4: Select gpmc_clk

    I suggest you to disable INPUTENABLE bit in this registers.

    Some GPMC chip-select pins have a pulldown resistor enabled by default In case of an application with several memories connected to the GPMC, for the memories connected to a chip-select whose internal pulldown resistor is enabled by default after reset
    (ncs1, ncs2, ncs3, or ncs4), it is necessary to disable this pulldown resistor before performing
    the first access to any memory. Otherwise, contention will happen because several memories
    will be selected at the same time.
    In the particular case of memory booting via the GPMC interface (memory device must be
    connected to the gpmc_ncs0 pin), it is not possible to disable any pulldown resistor before the
    first access.

    Best regards,

    Yanko

  • I've configure all of the GPMC pins, excluding GPMC_CS4, GPMC_CS7, GPMC_A25 and GPMC_WAIT[1:2], which are not available on the OMAP54xEVM. The "gpmc_noe_nre" pin is configured, and I do see activity on the pin. I also disabled all pull-up/down configurations for all output signals.

    The contents of the CONTROL_CORE_PAD0_C2C_CLKIN0_PAD1_C2C_CLKIN1 (0x4A002858) register is 0x40005 (after config), where the GPMC_CLK mode is 0x4 and the INPUTENABLE is disabled as you suggested. The lower 16-bit word is used to configure gpmc_nbe1 (mode = 0x5).

    There is no activity on J20-35 (GPMC_CLK). I also verified this on two EVM boards, so I'll continue reviewing my work. Thanks!

  • Hello Michael,

    Do you have any updates about your issue with GPMC_CLK?

    Could you provide your workaround if you solved this issue?

    Thanks in advance!

    Best regards,
    Yanko
  • Yanko,

    This was a caused by a minor syntax issue when configuring the GPMC_CSX registers. The GPMC is now working as expected.

    Thanks!