I'm trying to configure the GPMC clock to free-run after GPMC reset, but I'm not seeing any activity on the output pin (J20-35). There are many posts about this issue, but I'm curious if a continuous GMPC clock (non-gating) is supported in sync/non-multiplexed mode. In addition, I'm struggling to figure out why I can't see GPMC clock activity (at pin) during write operations. I can see the chip select and write enable, but no clock. I'm probing from the main expansion header, so there is no hardware interface connected to the GPMC.
The following CM registers show that the dependent clocks are active, which implies GPMC_FCLK is active:
1. CM_L3MAIN2_CLKSTCTRL = 0x103 ( RUNNING | HW_AUTO )
2. CM_L3MAIN2_L3_MAIN_2_CLKCTRL = 0x103 ( RUNNING | HW_AUTO )
3. CM_L3MAIN2_GPMC_CLKCTRL = 0x1 ( FUNCTIONAL | HW_AUTO )
The pad configuration is:
4. PAD_GPMC_CTRL = 0x104 ( PAD_MODE4 | PAD_PULL_DISABLE | PAD_PULL_DOWN | PAD_CELL_PWR_ON | PAD_INPUT | PAD_WAKEUP_DISABLE )
I successfully reset the GPMC, and then configure the GPMC_SYSCONFIG register again:
5. GPMC_SYSCONFIG = 0x8 ( FREE_RUN | NO_IDLE )
I then configure the CS0 in 16-bit synchronous non-multiplexed mode (NAND), and write to the base address continuously. Any ideas?