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Is it possible to turn off driver for DDR1_A15?

David Meixner
Expert 4010 points

My customer made a mistake on their board layout, and crossed DDR1_A15 and DDR1_A14 at the DRAM.  Due to the board layout, they can’t cut the trace at the DRAM.   The best option that we see is to drill the via at the processor for A15 and connect A14 to the termination resistor.  At this point, it will leave about a 1” stub.   Not good, but might work.

Another option that we wanted to explore is if the A15 and A14 lines can be turned off via the PINMUX.   There is no listed PINMUX for these pins, but we're hoping something can be done that is undocumented. The datasheet mentions most pads are set to MUXMODE 0xF by default, which is HI-Z, but it's not clear if that's the case for DDR pins.

The question that we really want to find out is if we can turn off the driver for DDR1_A15 via software while enabling the rest of the DDR1 interface.   If so, how is it done?

Thanks,
David

  • 0
    TI__Mastermind 29520 points

    Hello David,

    At first, Could you define which device your costumer use?

    I will explain you about MUXMODE configuration in DRA7XX device.

    There are no pinmux options for all EMIF signals. You can see in Table 2-2. Ball Characteristics in DRA7xx Data Manual.

    #Q: The question that we really want to find out is if we can turn off the driver for DDR1_A15 via software while enabling the rest of the DDR1 interface.   If so, how is it done?

    - You cannot turn off the driver for DDR1_A15 only. EMIF signals pass through DDR PHY. To Configure the DDR PHY-specific settings. Refer to registers of EMIF_DDR_PHY_CONTROL_1, and  EMIF_EXT_PHY_CONTROL_1 through EMIF_EXT_PHY_CONTROL_24.

    There are DDR PHYs and then DDR I/Os between each EMIF controller and external SDRAM. The EMIF controller, the DDR PHYs and the DDR I/Os work like a single unit to manage data exchanges to and from external memories.

    CTRL_CORE_CONTROL_DDRCACH1_0[17:16] DDR3CH1_PART5A_WD bit field enables the weak pull-up resistors for all 16 pads in the PART5A group. These are the ddr1_a[15:0] pads.

    CTRL_CORE_CONTROL_DDRCACH1_0[23:21] DDR3CH1_PART5A_I
    CTRL_CORE_CONTROL_DDRCACH1_0[20:18] DDR3CH1_PART5A_SR
    CTRL_CORE_CONTROL_DDRCACH1_0[17:16] DDR3CH1_PART5A_WD

    DDR I/O cells have the software controls which reside in registers of the CTRL_MODULE_CORE.

    Those registers can help you to control DDR1_a15 - impedance, weak driver and slew rate.

    Registers For Basic EMIF Configuration are:

    CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIG
    CTRL_WKUP_SECURE_EMIF2_SDRAM_CONFIG

    CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT
    CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT

    Best regards,

    Yanko