First of all sorry for posting this here but didn't find a fitting forum.
I'm looking for a way to measure the amount of data read/written from/to DDR memory on an ADAS Vision High SoC. In the document "ADAS_Superset28_ES1.1_NDA_TRM_vO.pdf" (SPRUHK5O) I found the 2 performance counters in the EMIF. These counters only count events which allows only a rough estimation of the size transferred between a master and memory.
There is another issue with the performance counters. I cannot filter the EVE_1 accesses. Using the MConnID of EVE_1 (0x10 << 2 = 0x40) the counter is not increasing. I've tried all ConnIDs from the TRM (even those don't making sense), but the sum of all individual masters is much less than the unfiltered result. Is there a ConnID missing in the TRM?
Is there a better way to monitor memory accesses? (maybe at L3 Interconnect or on a specific core such as C66xx and CortexA15)
Thanks in advance,
Roland