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Jacinto 6 - CPTS reset

Jakub Mielczarek
Intellectual 290 points

Hello,


How to properly reset the CPTS hardware on Jacinto? Should I wait some time after resetting it before I can use it?

Thank you,

Jakub

  • 0
    TI__Mastermind 29520 points
    Hello Jakub,

    Yes, you must wait some time before resetting.
    See the CPTS initialization sequence:
    1. Reset the CPTS module as - Clear the CPTS_EN bit in the CPTS_CONTROL register.
    2. Write the CLKSEL_RFT value in the CM_GMAC_GMAC_CLKCTRL register in the PRCM with the
    desired reference clock selection.
    3. Set the CPTS_EN bit in the CPTS_CONTROL register.

    See register - CPTS_CONTROL[0] CPTS_EN - Time Sync Enable - When disabled (cleared to zero), the RCLK domain is held in reset.
    0 - Time Sync Disabled
    1 - Time Sync Enabled

    The time stamp value is a 32-bit value that increments on each CPTS_RFT_CLK rising edge when CPTS_EN is set to 1. When CPTS_EN is cleared to 0, the time stamp value is reset to 0.

    CPTS module is in reset by following signals from PRCM to GMAC - L3INIT_RST or PRM_PWRON_RST.

    For more information about CPTS configuration see in drivers/net/ethernet/ti/cpts.c
    Best regards,
    Yanko
  • 0 in reply to Yanko Todorov-XID
    Intellectual 290 points

    Hello Yanko,

    Thank you for explanations. How long should I wait after resetting CPTS before I can use it?

    Best regards,

    Jakub

  • 0 in reply to Jakub Mielczarek
    TI__Mastermind 29520 points
    Hello Jakub,

    You must measure this time with your software and hardware.
    Please see section - 24.11.4.7 Software Reset
    CPTS does not have an option to be individually reset. This module has options for enable and disable. As I already said it uses global reset signal to GMAC_SW module - L3INIT_RST or PRM_PWRON_RST

    However, there are there are three CPSW_3G submodules that contain software reset registers (CPGMAC_SL1, CPGMAC_SL2 (SL_SOFT_RESET), and CPDMA (CPDMA_SOFT_RESET)). Each of the three submodules may be individually commanded to be reset by software.

    After all three submodules (in any order) have been reset and a read of each submodule reset bit indicates that the reset process is complete, the CPSW_3G software reset register bit may be written to complete the CPSW_3G module software reset operation.
    The description of software reset bit is:
    Software reset - Writing a one to this bit causes the 3G logic (INT, REGS, CPPI, and SPF modules) to be reset.
    After writing a one to this bit, it may be polled to determine if the reset has occurred. If a one is read, the reset has not yet occurred. If a zero is read then reset has occurred.

    Best regards,
    Yanko