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DRV2700EVM-HV500: output voltage ripple issues

Part Number: DRV2700EVM-HV500
Other Parts Discussed in Thread: DRV2700,

Hello, I'm experimenting with the DRV2700EVM-HV500 evaluation board to understand if i can drive a piezolectric actuator with a DRV2700.

The actuator requires voltages up to 500V and the circuit seemed to be perfect. The actuator capacity is about 200nF.

The problem is that the high voltage output exibhits a huge amount of ripple (50Vpp with only about 20V setpoint!!!) with no load (with only the stock 1nF capacitor mounted on the PCB). If the capacitive load increases the ripple decreases, changes in frequency, but remains quite high. You can actually hear the noise from the piezoelectric element which vibrates at that frequency. Is this evaluation board broken in some way or it's a limitation of the flyback configuration of the DRV2700 ?

I run tests both with DC and arbitrary waveform output with the same results. I tried different types of capacitive loads, from 1nF  to 300nF.
The ripple is higher at lower output voltages and lower capacitive loads.


Here the waveforms relatives to 10%, 50% and 90% duty cycle of input signal for 2nF and 200nF capacitive loads.

2nF, 10% duty-cycle input signal:

2nF, 50% duty-cycle input signal:

2nF, 90% duty-cycle input signal:

200nF, 10% duty-cycle input signal:

200nF, 50% duty-cycle input signal:

200nF, 90% duty-cycle input signal:

  • Hi Andrea,

    Your post has been moved to the Haptics Forum for better support.
  • I just noticed that i've submitted the 200nF waveforms two times!

    Here are the waveforms for 2nF...

    2nF, 10% duty-cycle input signal:

    2nF, 50% duty-cycle input signal:

    2nF, 90% duty-cycle input signal:

  • Hi Andrea,

    There will always be a little ripple on the output due to the flyback nature of this design. However, the ripple can be optimized to the desired output voltage by adjusting the flyback circuit, specifically R9, R23, C13 and C21 using the "down/down" setting. With the default EVM design, the ripple should be optimized for 500Vp drive. Figure 15 in the user guide shows the small ripple at 500V drive with 20nF load.
    Can you clarify what you mean by "50Vpp with only about 20V setpoint?"
    Also to confirm, your load conditions are 2nF or 200nF driving to 500Vp? What type of signal do you want to drive, for example sine wave or square wave? And what frequency?
  • Hi Kelly, thanks for your answer.

    Actually I'm using the configuration with the jumpers "up/up" (158V max) for ease of measuring. With the jumpers "down/down" (500V max) the ripple is very similar, not so much better.

    In my application I want to drive the piezo actuator in consecutive stable positions. So I'm going to generate the setpoint (voltage reference...) with a PWM signal with a given duty-cycle. Adjusting the duty-cycle the microcontroller can control the elongation of the piezo element.
    The piezo element is attached to a thin layer of glass (part of an adaptive lens) which is bent to obtain a variable focusing power of the lens.

    To be able to do that, I need a very stable output from 0 to 500V. Is it possible with this kind of circuit or i can only optimize it in a small range of output voltage? After carefully reading the datasheet I'm now thinking that this behaviour is caused by the hysteretic control strategy...am I right?

    PS: With "50Vpp with only about 20V setpoint" I mean that with a PWM input signal which should produce a 20Vdc output (according to it's duty-cycle), I get that horrible sawtooth-like waveform with 50Vpp of amplitude. I need almost constant or negligible ripple across the full 0-500V voltage range.


  • I also tried to replicate the behaviour shown in Figure 15 of the DRV2700EVM-HV500 datasheet. With 22nF load  and a square wave input signal I obtain the following waveform (0-500V levels, switches set to "down/down"):

    As you can see the rise/fall times are way longer than those shown in the reference design datasheet! I get more than 2.5ms rise/fall times instead of 1ms.

  • Hi Andrea,

    Thanks for the clarification and information.
    Correct, the ripple is due to the hysteretic control of the design described in section 4. For that reason, it can only be optimized for small voltage ranges for each resistor/capacitor feedback combination. For your design, you would need to optimize the feedback network and then control the smaller steps by changing the input PWM signal. You still want to keep the output near full scale to minimize the ripple.
    In the above waveform, the ripple seems to be very small as expected.. What voltage rail did you use for this design? I can look into the rise and small time discrepancy.
  • Yes, at 0 and 500V setpoints the ripple is fairly low (about 1-2%). Unfortunately we need this behaviour in the full range 0-500V.
    I think we'll adopt another solution.

    Thanks for your help anyway!

  • You're welcome. Sorry that our design doesn't meet your needs and thanks for posting to our E2E forum.