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DRV2700: Design method in flyback mode

Tomoaki Yoshida91
Genius 5255 points
Part Number: DRV2700

Hi team,

Our customer is considering to use DRV2700 in flyback mode.

In order to decide constants and part numbers, please tell me the following points.

#1 Inductor and Rext

It is written to limit the current limit so that the inductor does not saturate in the data sheet.

Looking at the DRV 2700 EVM-HV500, the current limit seems to be set at 1.4A, but the saturation current of the used inductor seems to be 0.6A.

How should we decide the inductor and current limit?

#2 OFF surge protection circuit for SW terminal

In a general flyback circuit, snubber circuits are often seen to protect IC from the negative surge when the SW terminal is OFF.

If the current value and the inductance value satisfy the requirement, since the SW terminal voltage will not exceed absolute maximum voltage, can I think that it is not needed snubber circuit?

Since we want to judge whether or not a snubber circuit is necessary, we want to know whether it is clear that it is not necessary.

#3 Pulldown FET

What kind of rated FET should be chosen when selecting a pull-down FET?

I think that we should choose a product rated higher than the maximum power consumption of FET, but please tell me how to calculate maximum power consumption for FET.

Best regards,

Tomoaki Yoshida

  • 0
    TI__Expert 8701 points
    Hi Tomoaki,

    1. This inductor was chosen based on size constraints and the current rating is not sufficient. The inductor or current limit in this design should be changed. Please select a current limit that will not exceed the inductors current rating.

    2. For this design, we did not think a snubber circuit was necessary. In a production design, the customer can determine if the additional protection is needed and implement a design accordingly.

    3. This FET has additional resistors added to the source, drain, and gate for protection. The source resistor will lower the Vgs as the current increases in order to protect the FET from over current. The drain and gate resistors will protect from fast falling transients when a short to GND occurs. The FET should be rated for the max output voltage. The FET chosen here has a max pulsed drain current limit of 90mA; with the additional drain/source resistance the current should not exceed 50mA.
  • 0 in reply to Kelly Griffin
    Genius 5255 points
    Hi Kelly-san,

    Thank you for your support.
    I told the customer to design according to your advice.

    Best regards,
    Tomoaki Yoshida