I am trying to capture the LVDS data streams and deserialize with Altera's FPGA (Cyclone 4 speed grade C7).
I am wondering if LVDS output from AFE5808 has any overhead( like start and stop bits ) per frame of data transmission? Where can i find out more on this information?
Thanks in advance.
No, AFE5808 doesn't have any overhead for LVDS transmission. depending on the ADC CLK, the output data rate is 14*CLK.
HiI just bought an AFE5808 evaluation board, and an Altera FPGA, and also the TI's ADC to HSMC bridge. I was hoping to use Altera's FPGA as a high speed deserializer.I know there is a high speed deserializer board based on Xilinx FPGA which is provided by TI, but for some reason i would like to stick with Altera's FPGA.Since a bridge from ADC to HSMC is provided by TI, I'm wondering if there is any example verilog code provided by TI that i could use for Altera FPGA? Thanks.Michael
TI doesn't offer FPGA code, which should be obtined from the Xilinx application note xapp866. can you leave you email and we can discuss further further? Thanks!
you can email me at email@example.com
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