I have a few questions regarding the AFE series ADCs. My application isn't exactly medical ultrasound, however it is close.
I'm using ultrasonic transducers to do time of flight measurements. I'm in the relatively low frequency range (40 Khz ish). I'm using Piezoelectric transducers, with a high channel count. I do some several national instruments DAQs at my disposal, and i'd like to combine the TI AFE chip and the NI-DAQ to create a cost effective lab setup. Eventually i'd like to move away from the NI-DAQ but i think they have a place for now. Here is my idea.
I understand (and i could be completely wrong here... that happens about twice a days at least. heheh) that the Analog front end chips are just a one-stop shop for the analog receive part of the an ultrasound setup. So all i have to do is hookup the transducers to the chip's input. I understand that the AFE will take for the signal conditioning (which would other require a charge amp) and the setup of the process until the ADC and output in LVDS. Is that right ?
Unfortunately I don't have a way to read LVDS. i bought myself (using my own money and not even project money) a MSP430 recently and maybe that would be used to interface the 2. However i had a little idea that might avoid that extra bit (which i'm sure for someone like me would take a long time).
My NI-DAQ is a 9403. It has the capability to of digital i/o at about 160 KHz (which is far far below the AFE but enough for me). Here's my question.
Could i setup a clock on the ADC that is 160 kHz. And then record the LVDS data feeds at a 160 kHz through the digital i/o. And process that Digital input to "read" the LVDS output from the DAQ.
I know its a weird setup, and it might be just completely crazy. Either way any idea on a cheap way to interface the AFE with the PC ? Even if i use this setup for now, i'd like to move away the NI-DAQ in the future. Ideally i'd like to have just one custom made box.
Thanks so much for reading.
Have a great night and/or weekend.
So i've been reading up on LVDS and i think i made a mistake. The LVDS output cannot be read by a digital i/o at all. It needs to be read by an analog input. Is that correct. I have analog input channels as fast as 100 KHz. each would those allow me to read the output of the AFE at 100 KHz. or would i be limited to a lower frequency (perhaps based on the nyquist condition) ?
Could i potentially hookup the 8 LVDS outputs to another ADC (maybe the ADS 800 for parralel) or an SPI out ADC and use that to read the LVDS ? Just a thought. Man i love this forum. My ideas are actually coming out on paper (screen) rather than staying in as voices in my head. lol.
So after some more reading i found this.A serializer/deserilzer.
Using this i could essentially read the LVDS data in 14bit. So i my question for this edit is, could i control the ADC sampling rate and limit the data produced by the ADC. i think i could interface the 14 bit parralel to some MSP430 uController, but i doubt it could handle the large quantity of data if i sample at 50 MSPS.
Thanks for reading.
To get ADC output data, the LVDS interface is the only way to do it, however the FCLK (Frame clock) rate is 10MHz minimal to make AFE5804 internal PLL to work; this means that the 160KHz sampling rate will not work with AFE5804.
Any suggestions for a microcontroller or something that could handle the LVDS input at 10+ MHz.
Anything that would allow me to collect data using a USB would be great.
I think i might have found a solution.
Can someone confirm that this will work ?
1. Use the AFE5804 untill the ADC out. Get LVDS out.
2. Use this to convert from LVDS to LVTTL
16-Channel LVDS Driver/Receiver Evaluation Module
3. And then sample the lvttl using this.
Thats a 4-channel Digital I/o module capable of 20 MHz.
Do you guys think this might work ?
I do not know it will work or not without doing it. Theoretically, your approach is fine. Have you ever tried TSW1250EVM supported by TI? TSW1250 deserialized the LVDS data from AFE5804 and send to data to PC. The heart of TSW1250 is a XILINX FPGA. I believe it is cheaper for your application.
I've spent some time looking at the TSW1250EVM.
I have a few concerns.
1. One of the threads on e2e talked about the tsw1250 gui only being capable of capturing 1 channel at a time. Is there a way to bypass this limitation.
2. The tsw1250 documentation list a 65k buffer for the FPGA. Does that mean it can only capture data 65k long. I'd certainly want longer dataset.
Am i misunderstanding something or are these actual limitations of the tsw1250EVM
[Q] 1. One of the threads on e2e talked about the tsw1250 gui only being capable of capturing 1 channel at a time. Is there a way to bypass this limitation.
[Allen Answer] You are correct. At the present time only 1 channel at a time. We will be developing multi-channel capture option soon.
[Q] 2. The tsw1250 documentation list a 65k buffer for the FPGA. Does that mean it can only capture data 65k long. I'd certainly want longer dataset.
[Allen Answer] : 65k is the maximum memory size of the FPGA. There is no way to increase, however we will be developing an option to bring the serial data to the headers on board, by then you can use a logical analyzer to capture at any size you want.
Are there any other High Speed deserializers you would recommend ? The option of using the logical anyalyzer introduces just another piece that i'd prefer to to avoid.
How about something like this
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