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AFE5804EVM clock problem

Hi everyone,

I want to use an AFE5804 in an ultrasonic visualisation project so i bought an evaluation module to do some testing.
My plan is to use an FPGA to capture the serial data from the AFE5804 and deserialize it. For this i would like to use the 40Mhz clock from the AFE5804 to drive the FPGA.

But when i measure the clock (LCLK) from the AFE5804 it is not wat I expected, The duty cycle is no where neare 50% and the frequency is only 400Hz and not constant.
I measure directly on the connector whit a scope (1GHz, 4GSa/s) a screen capture is added. The FCLK lies around 4000Hz.

If somoene can point me in the right direction i'd be very grateful.

Hans Blockx

2 Replies

  • Hans,


    I am the Applications engineer for TI Medical.  I will look into this today.




    Chuck Smyth

  • Hans,


    I apologize for the long delay.  Were you ever able to solve your problem with the LCLK?  It should definitely be 50% duty cycle. Secondly, if you run the input clock at 40 MHz, then LCLK should be 6X that, which is 240MHz.


    1. What is your probing situation like when you probe LCLK?  Are you using a High impedance probe or 50ohms directly into the scope?

    2. Do LCLKP and LCLKM have similar behavior?

    3. Are running the device in SDR mode or DDR mode? SDR mode is enabled by setting the EN_SDR bit, and results in an LCLK running at 12X instead of the default DDR mode, which is 6X. If you are running at a 40MHz input clock in SDR mode you could be experienced the frequency ceiling for the LCLK.  40Mhz  X  12 = 480 MHz, which is fast and according to the AFE5804 Datasheet:

    "The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high."


    FCLK should be running at the input CLK frequency and LCLK should be at least 6X faster.




    Chuck Smyth