I would liked to know which technology is used on the entry of the VSP1221(0.35µ or 0.5µ) ?
I found that it was a technology LinEPIC 33A12 and i need to know if i can apply a voltage of 3.7 to 3.8V during 1 ms on the entry DIN (or PIN) of the VSP1221. On the first stage of the entry we can found a transistor CMOS protected by a diode...
Thanks for your answer.
The VSP1221 is a 3V device. The maximum voltage applied to any pin should be VDD + 0.3V or approx 3.3V.
The diode is intended to protect the input transistor, but eventually it will breakdown if 3.8V is repeatedly applied. I suggest modifying your circuit to prevent the 3.8V spike.
Thank you for your answer,
In the datasheet of the VSP1221, the resistance Ron of the switch used for the clamp on the analog entries is not indicated. Can you give me an order of magnitude for this resistance or its exact value please ?
I don't have an exact value. Typically about 250 ohms is a reasonable estimate.
I am at the end of my survey of the clamp circuit of the VSP1221, before passing to more complex characterizations of the component, I would like to know which maximum value of current can absorb the amplifier which provides the VDD-0.8 to the clamp circuit? During a test, i applied 14,34 mA during 100µs and the clamp isn't destroy....
do you have a sheet more complete than the datasheet of the component ? we haven't enough data to use the component in difficult conditions.
Once again, thank you
The device is designed and tested for ESD (Electrostatic Discharge) resistance. This is typically a few kV at very low currents. Beyond that, do not exceed the Absolute Maximum ratings found in the data sheet. The data sheet posted to the TI web site is the latest data sheet.
The VSP1221 is tested to withstand eletrostatic discharge, Information on ESD test procedures can be found at
http://en.wikipedia.org/wiki/Electrostatic_discharge under the section "Simulation and Testing".
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