This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • Resolved

LM98620 eval board schematic

Dear Tiers,

One of our customer finalized to use TI LM98620 ADC for the CCD frontend.

The datasheet refers to development board schematics & layout (page 59 & 64) for guidelines.

Can anyone please share the schematics for LM98620 evaluation board.

regards,

syed

  • In reply to Mohammed Abuhendi:

    Hi Mohammed,

    I've uploaded whatever I had on this EVM that resembles Gerber files in the original location zip file:

    3580.0131.LM98620 EVM.zip

    Hopefully this is what you are looking for?

    Sorry, I don't have anything else if this is not what you want.

    Regards,

    Hooman

  • In reply to Jim Brinkhurst84999:

    Hi Jim,

    1. When using black  level calibration (automatic method), CDAC and  FDAC enable mode should be used after power up calibration and FDAC only mode during normal scan operation. Is my understanding correct. Can Auto black loop Enable in register BLKCLP_CTL0 (0x23 bit 2) kept HIGH always.

    2. When using white level calibration (automatic gain control), AGC_ON bit in register AGC_CONFG (0x28 bit 0) is set using serial interface(AGC_ONB is always HIGH. AGC_ONB polarity selected as active low). Should we write AGC_ON LOW from serial interface after white loop is complete or will it get cleared automatically after white loop is complete.

    Regards

    Prasanna

  • In reply to Prasanna Ganapathi:

    Hi Hooman,

    Can you please clarify my above questions.

    Regards

    Prasanna

  • In reply to Prasanna Ganapathi:

    Hi,

    Can anyone please help.

    Regards

    Prasanna

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.