LM98725: SH1 output doesn't toggle during CCD readout. phiA, CP, RS toggle, but look bad

Part Number: LM98725

Summary:

All signals toggle indefinitely except SH1. There is no "readout window" I can catch on the scope by triggering to SH1. Please help.

Details:

I lock the registers (start CCD readout), and watch SH1, PHIA1, PHIB1, CP, RS with scope (high-Z), not loaded at all.

When I toggle "SH1 active" register field on/off in unlocked state, the corresponding output changes DC value from 0 to 3.3V and vice versa.

This means, I look at the proper output. But it doesn't toggle during locked state.

Total current consumption: locked: 124mA, unlocked: 116mA

The registers I touch during configuration:


Signal outputs (5 MHz input clock):

My test circuit based on datasheet circuit:

7 Replies

  • Hello Rom,

    We have received your inquiry about the device LM98725. I will check with the team and will get back to you soon.

    Best Regards


    Praveen Aroul

  • Hello Rom,

    What clock frequency are you supplying to the LM98725? Page 26 in the datasheet says that Mode 1 can only take a maximum input clock frequency of 25 MHz.

    Can you please check to see if there is some kind of averaging function or filtering function turned on for your oscilloscope? Also, can you double check that you have eliminated all sources of coupling and grounded your probes correctly?

    James Lockridge

  • In reply to James Lockridge:

    Hello, James.

    I used 1, 5 and 10 MHz clock input without major difference.

    The plots are provided for 5 MHz clock.

    I used no averaging on the signal. My scope has 50 MHz analog BW and freshly calibrated probes.

  • In reply to Rom Yaz:

    Rom,

    What kind of clock source do you have going to your INCLK+/- pins (LVDS or CMOS)? Are you following the external clock layout requirements on the bottom of page 16 in 7.3.6.1?

    James Lockridge

  • In reply to James Lockridge:

    Good day.

    The clock is configured as single ended:

    • I push clock through CLK+ input port.
    • CLK- input is grounded by a jumper.
    • I did not populate the 50 Ohm resistor.
  • In reply to James Lockridge:

    Hello, James.

    Do you have any ideas or update for me?

    I generated the clock with a 3.3V microcontroller.

  • In reply to Rom Yaz:

    Hi Rom

    If you've only written to those registers on page 0 and page 8, the CCD Timing outputs won't be providing useful clocking.

    Please try loading the following register settings (followed by setting the register lock bit) to see if that changes the waveforms see on the outputs.

    /cfs-file/__key/communityserver-discussions-components-files/239/CIS-Example-Mode-1-one-color-sequence.dat

    Changes made:

    • Enable CMOS data clock at SH12 (Page 0 Register 5 Bit 5)
    • Setting sample and clamp timing to values in-range for Mode 1, Sample and Hold (Page 0 Registers 08 to 13h).
    • Enable one SH interval for 15 clocks (Page 3 Register 0)
    • Set SH1 high during SH interval 1 (Page 5 Register 0 bit 0)
    • Setting PHIA, PHIB and RS and CP on/off timing for 50% duty cycle (Page 6 Registers 00 to 1Dh)
    • Make SH1 turn on at pixel 500 and off at pixel 1000 (Page  Registers 00-03h)

    The file format doesn't include a Page number, but instead has all registers in series with each page being 1F registers long.

    Best regards,

    Jim B