hi~ i have a qustion for AFE5808 about "deserialize" we used Xilinx FPGA EVM -ML605 (vritex6) and AFE5808 EVM to test deserialize when i used TI's EVM GUI to set command " Custom patten" for test patten => deserialize result is correct but when i set command " Ramp" for test patten => deserialize result have noise , like bitslip ...
so i don't understand if my FPGA deserialize module is right why "Custom patten " is correct but "Ramp patten " is error ?
It sounds like the timing does not meet setup and hold time of the FPGA. What Custome pattern do you use? Can you send image of the Ramp test to me?
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