Trying to generate timing for a S11510 CCD. Pixel binning is done separately, then SH_R is triggered to start the shifting out of data. Mode 1a is used at INCLK=250kHz. The weird phasing requires the final shift-gate pulse and reset pulses to be generated 1/2 pixel offset from main pulses. This is requiring that the PIX edges sometimes be set to "stop" before they "start" (See diagram) and that the last two PIXs be offset by 1 pixel (using off GB). I cannot seem to get the chip to co-operate and I am wondering if what I am trying to do is even possible with this IC. Are there any required programming sequences or parameter limits that must be observed?
I don't think it will be possible to create the necessary timing for this sensor using the LM98714. The low INCLK frequency of 250 kHz will also be a problem. The minimum ADC frequency for this device is 5 MHz due to the internal PLL used to generate on-chip timing.
Given this combination of complex clocking requirements and low sample rate, you may need to look into a programmable logic device to create the CCD timing signals, along with an AFE like the VSP3010, VSP3200 or VSP3210 for signal capture.
I hope this is helpful.
Nice to see I've probably wasted a PCB generation. Now, just *where* in the documentation is this 5MHz minimum speed mentioned? Didn't anybody think it critical enough to place in the datasheet?
You are correct. That specification is definitely missing from the LM98714 datasheet at www.ti.com. It is included in the internal TI proof document I referred to when answering your question. I am trying to track down why it is missing, and will get the web document corrected.
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