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AFE5805 LVDS TEST PATTERNS and LVDS receive

haiteng wu
Prodigy 20 points
Other Parts Discussed in Thread: AFE5805

I set EN_RAMP to "1", cause all the channels to output a repeating full-scale ramp pattern, and use altlvds_rx in FPGA to receive the ramp signal, I can see the ramp pattern in Signal Tap,but the data is not all right, regularly three datas are the same after three datas increments as the figures below show.

When I put sine signal to AFE5805 input pin, the same phenomenon happens.What causes this phenomenon,AD converter or LVDS receive ? 

  • 0
    TI__Expert 6320 points

    Haiteng,

    It looks like your bit [0] and bit [1] get stuck for two cycles.  I have never seen this phenomenon in the AFE5805.  What is your FPGA solution? Please try some of the other test patterns like Toggle.  Also, please slow down clock if you are using an external clock.

    Thanks,

    Chuck Smyth

  • 0 in reply to Chuck Smyth
    Prodigy 20 points

    Hi,Chuck,

    I use Altera IP altlvds_rx to receive lvds data from AFE5805, deserialization factor is 6, write the rx_out[5..0] into FIFO with rx_outclock(100M), and read from FIFO using 50M clock to splice a 12-bit data. Input some pulses on rx_channel_data_align[0] to realign byte order. I watch the FIFO output signal in Signal Tap, and the result is showed in the figure above. As you suggested, I try the toggle with two codes 0xAAA and 0x555, the phenomenon is the same. I also slow down the input clock of AFE5805 to 15M, there is still no improvement.

    Thanks!

    Haiteng

  • 0 in reply to haiteng wu
    Prodigy 40 points
    Hi,Haiteng,
    the output FCLK of my AFE5805 don't have frequency output, I doubt with my configuration data which may be wrong,could you share the configuration data with me?
    Thanks!
    chao zhu