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AFE5808 Clock Input

Mehdi Tamehi
Intellectual 450 points
Other Parts Discussed in Thread: AFE5808, CDCLVD1204, CDCLVP1204

The AFE5808 datasheet talks about compatible LVDS clock inputs:

 

>AFE5808 page 61 has the LVDS wiring configuration

>AFE5808 page 11 "ADC INPUT CLOCK" says LVDS "Typ" Vpp=0.7V

>AFE5808 page 11 "ADC INPUT CLOCK" says LVDS "Typ" Vcommon=1V

 

In this case the AFE clocks would be driving by a CDCLVD1204 (2V5 supply)

 

>CDCLVD1204 page 5, VOD says Vpp between 250mV and 450mV

>CDCLVD1204 page 5, VCM says 1.1-1.375V Vcommon

 

The CDCLVD1204 clock outputs are AC-coupled to the AFE, so the 1V for Vcommon should be fine. However, the AFE5808 input spec for LVDS peak-to-peak level "Typical" of 700mV is quite high compared to the CDCLVD1204 peak-to-peak outputs. 

 

As I look into LVDS typical levels, they average 350mV. To reach 700mV, LVPECL seems to be the standard. However, the current design is quite committed to LVDS clocks and redesigning LVPECL will introduce unknowns (even though technically we could use a CDCLVP1204 - but not sure about the supply etc..).

 

Is it actually possible to go with that LVDS-level clock inputs into the AFE5808 (typical Vpp of 0.350V) when the AFE spec for Vpp says 0.7V but also says LVDS-compatible?

 

Thanks,

  • 0
    Intellectual 450 points

    Also I need to know about the LVDS signal impedance. The datasheet says "controlled" impedance but doesn't give a number. Would 60 ohms be an ok value?

    Thanks,

  • 0 in reply to Mehdi Tamehi
    TI__Expert 6040 points

    the LVDS voltage depends on driving current vs termination R. in past TI ADCs, we assume +/-3.5mA @ 100ohm load. it appears to be 0.7Vpp. when driving current is reduced, LVDS votlage is reduced as well.  of course, the driving capability will be less. 

    0.3Vpp to 0.35Vpp LVDS can work as well from our experience. 

    as our datasheet shows, AC coupling is required  considering the 1V VCM votlage. DC cuopling can be applied only when the LVDS driver's VCM is the same as AFE's. 

    LVDS is  terminated at 100ohm deferentially by default. so you can use 100ohm diff impedance in PCB layout. some FPGA venders have different internal term R values. you can discuss with FPGA venders.

    Thanks!