I am new to LM98714
so pls help me to initialise LM98714,
Am trying to initialise the device in CMOS mode and with out CCD timing generator, my INCLK is 50Khz.
I've attached a register map for the LM98714 (but I don't have any details for the conditions / settings to share with you).
You may have mis-typed the INCLK (50kHz). Here are the INCLK values in the MHz range:
In reply to Hooman Hashemi:
Hi Hooman Hashemi
Thanks for your feedback..
My INCLk is 50Khz only ,
in the above table for INCLK = ADCLK minium clock is 5MHz
but for INCLK = PIXCLK minium clock is mentioned in the table.
and the settings what you have provided is for which sensor CCD/CIS & in which mode CMOS or LVDS.
In reply to Govind katti1:
As you have noted, the LM98714 would not work with INCLK of 50kHz. May be you can explain what you are trying to do and what dictates your low INCLK frequency and we will get back to you with your suggestions.
Hi Hooman Hashemi
As you have suggested, i made INCLK= 8MHz, and initialized the LM98714 according to the figure 64.
My configuration details are given bellow.
Main Configuration 0 = 0xF1.(Mode 3 in forward mode and one color sequence).
Main Configuration 1 = 0x05.(O/P format is CMOS, INCLK = ADCLK).
Main Configuration 2 = 0x08.(Device active,O/P enable,Device fully powered).
SH Mode = 0x80( SH o/P pin to tristate,SH source select to external).
CMOS Data Mode = 0x20.(CLK10 is configured as CLKOUT).
Am not using the CCD timing generator so i kept all other registers to default.
After all this configuration, starting the scan by using start scan bit in
Main Configuration 2 = 0x01.
Am polling the ready bit after start scan, and it is working as expected (shown in fig 64).
I am observing some pulses on output pins but am not getting any pulses on CLKOUT pin.
I think the following might be your current issue with the LM98714:
1. You may have to do additional register settings to get the CLKOUT.
a) Status Bit Enable: Set the Register Page 2, Address 11110, CMOS Data Mode Status Bit Enable, bit 5 to "1" (CLK10=CLKOUT), as shown below:
b) Tristate Override Removal: You may have to additionally do the following to Register Page 3, address 00100, "Output Mapping CLK9/CLK10" bits [3:0]: Change to anything except 0000, as shown below:
Please try these changes above and let me know if you are still having issues.
Thank you for your feedback.
I made changes suggested by you.Now i am able see some pulses on CLKOUT pin and i captured some images from oscilloscope and same is shown bellow.
Am observing some noise on the CLKOUT pin (fig 1).
When i expand the time base ie shown in fig2.
Frequency and period details are shown in right bottom corner of each image.
We are trying to think of reasons why you are getting the "noise" on your CLKOUT during the "hi" or "1" state and so far we do not have answer yet!
I wanted to ask you to make sure that the board you are using has adequate supply decoupling caps and ground planes to make sure you have a low inductance ground path.
We'll discuss this further internally tomorrow and get back to you to see if we can find the source of the waveform noise.
Hello again Govind,
Can you share the schematic your board (at least the LM98714, clocking, power supplies portion)?
Here is my private email if you like to send it that way:
Thanks for the schematic that you emailed me. I don't see anything big standing out, but I have some comments:
1. Wrong Period: I had noticed that the CLKOUT had a 146Hz repetition rate! Your problem is not just the "disturbance" on the high side but in fact completely wrong waveform. Repetition rate should either be the same as your INCLK (8MHz) or some multiple of it.
a) Can you confirm that RESET_bar (CIS_0EB) is not being toggled at this rate which it should not be. Can you please confirm?
2. Schematic dot missing: Please make sure the VR pin is tied to C29 (schematic dot is missing). Also, please confirm that DVB pin is only tied to C34 (and not connected to 3.3V). I'm hoping that your board layout does not get confused by this drafting issue?
3. CLKOUT Probing things to try: Did you try the experiments (with regard to the way the CLKOUT is being probed)?
a) What is nature of the oscilloscope probe you are using (e.g. normal 10Mohm 10x scope probe?, etc.)
4. Waveform Capture(s): Can you capture the following waveforms simultaneously and share?
INCLK+, CLKOUT, RESET_bar
5. Missing large (4.7uF) caps: There are several 4.7uF caps (called for in the datasheet) that are missing on the following pins:
VA, VCLP, VD
You have shown 10uF caps on your schematic page 3 and I wonder if these are close enough to the LM98714 (they should be) to be effective?
I would place the 4.7uF caps noted next to the pins as well as on 3.3VDVAC and 3.3VADC.
6. Ground Separation not needed: You have kept AGND and DGND separate on your schematic and I think you use 0ohm resistors (R14 and R15) to tie them together probably near the LDO? Our general guidelines is to not separate the analog and digital grounds and have them tied to each other near the device. Is this something that you can implement and try (or at least use a scope to verify that the two grounds next to the LM98714 do not have large / fast transients)?
Please let me know your findings from the list above.
The register dump has registers from address 0x0 to 0xBF.
But as per datasheet LM98714 has only 5-bit address.
Do the MSB 3-bit address from register dump represent page no.
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